Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors

Abstract

Polysilicon thin-film transistors are of great interest for their application in large area microelectronics and especially for their circuit applications. A successful circuit design requires a proper understanding of the electrical characteristics and in the present work some specific aspects related to the hot-carrier induced electrical instabilities are presented. In particular, generation of interface states near the drain junction occurs when the devices are operated for a prolonged time in the so-called kink regime. In the present work we show both experimentally and by numerical simulations how the presence of such interface states affects the electrical characteristics. Furthermore, a novel simple method is proposed to extract, from the analysis of the sheet conductances, the interface state density. The hot-carrier induced interface state density relative to the present devices shows a featureless continuous distribution. Reduction of the generated interface states is observed if trapped holes are annihilated by electron capture. These results suggest that the interface states are induced by the presence of trapped holes, in agreement with similar data reported for c-Si metal–oxide–semiconductor structures.

Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors

“…In Fig. 4(a), are shown the transfer characteristics measured in a p-channel TFT before and for different times during bias-stress performed at V g (stress) À V t = À4 V and V ds = À14 V. As can be seen an appreciable transconductance degradation occurs due to hot carrier effects and has been attributed to the formation of interface states at semiconductor-insulator interface close to the drain junction where the electric field is maximum [7]. Let us now discuss the behavior of the output characteristics of p-channel TFT after bias-stressing.…”

“…These effects are induced by the presence of intense electric fields at the drain junction, determined mainly by the abruptness of the lateral doping profile. Extensive investigation of HCE in polysilicon TFTs has shown that, similarly to c-Si MOSFETs, the device degradation is controlled by the formation of interface states and oxide traps and charge injection in the gate oxide [7,8]. Recently, it has been also proposed that hot carrier induced defects could be generated at the grain boundaries creating a damage region close to the drain junction [8].…”

Asymmetric fingered polysilicon p-channel thin film transistor structure for kink effect suppression

“…Kink-effect and hot carrier instabilities are related to impact ionization at the drain junction induced by the presence of intense electric fields at the drain junction, determined mainly by the abruptness of the lateral doping profile. In particular, it has been shown [4,5] that in polysilicon TFTs, similarly to c-Si MOSFETs, the device degradation is controlled by the formation of interface states, oxide traps and charge injected in the gate oxide. It has been also proposed that hot carrier-induced defects could be generated at the grain boundaries, creating a damaged region close to the drain junction [5].…”

Dopant‐activation and damage‐recovery of Ion‐shower‐doped poly‐Si through PH3/H2after furnace annealing

“…As the channel length is becoming shorter, device reliability of LTPS-TFT's must be taken into account [7,8].…”