Determination of CPU use conditions

Kwasnick, R. F.; Papathanasiou, Athanasios; Reilly, Matthew; Rashid, Al Mamunur; Zaknoon, Bashir; Falk, John H.

doi:10.1109/irps.2011.5784455

Cited by 25 publications

(10 citation statements)

References 5 publications

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“…Four use scenarios [2] are considered in this paper, namely, corporate, general usage, office work, and gaming. The use scenarios have different percentages in active, standby and sleep modes, as shown in Fig.…”

Section: Memory Lifetime Analysismentioning

confidence: 99%

“…The electrical stress and thermal profiles for the memory were collected by the framework described in Section 3. The realistic use scenarios [2] further modify the stress profile of each cell. The electrical and thermal profiles, process parameter variations, together with the lifetime models from Section 2, were then used to analyze the performance of each SRAM cell within the memory.…”

Section: Memory Lifetime Analysis For Bti and Hcimentioning

confidence: 99%

“…By this method, the lifetimes of all the cells in the memory due to each wearout mechanism are determined. Moreover, the lifetime estimates take into account realistic use scenarios [2] which include active, standby, and sleep modes. The paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

“…The percentages of different use scenario in active, standby and sleep modes[2]. The degradations of all the performance metrics due to NBTI/PBTI.…”

mentioning

confidence: 99%

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Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Liu

Chen

Kim

et al. 2015

Microelectronics Reliability

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a b s t r a c tA framework is proposed to analyze the impact of both Front End of the Line (FEOL) and Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory by running a variety of standard benchmarks. Combining the stress/thermal profiles and the wearout models, the performance degradation of SRAM cells for each wearout mechanism is studied. The lifetimes of the SRAM cells are then obtained when the performance metric degrades to a predefined threshold. The proposed work introduces a method to deal with the large volume of SRAM cells whose stress is non-uniform by partitioning the SRAM cells into different stress states, and generates the lifetime distribution of the memory system due to each wearout mechanism by combining the lifetimes of the cells, whose distributions vary with the stress received. Seven wearout mechanisms have been studied, namely, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate oxide breakdown (GOBD), backend dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV).

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Section: Memory Lifetime Analysismentioning

confidence: 99%

Section: Memory Lifetime Analysis For Bti and Hcimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The percentages of different use scenario in active, standby and sleep modes[2]. The degradations of all the performance metrics due to NBTI/PBTI.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Liu

Chen

Kim

et al. 2015

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…Modern energy efficient product features operate at varying frequencies and voltages in response to demand to conserve power which results in changes to the thermal environment [2]. For example, in Figure 2, the reliability of a device with a local hot spot in sub-system-B can be impacted by the ability to remove heat using a heat sink and fan.…”

Section: End User Environmentmentioning

confidence: 99%

Package reliability and performance trends in an era of product integration

2014

2014 IEEE International Reliability Physics Symposium

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Product differentiation is expected to accelerate and will encompass integration of product functionality into single and multiple die on package as well as multiple die/packages on board. Novel packaging designs will lead to incorporation of new materials and processes from which a comprehensive understanding of operating conditions at system and subcomponent level will be required to ensure reliability at minimum impact to cost & performance. Reliability tests, models and analysis must evolve to encompass emerging failure mechanisms and geometric effects not considered when standards were originally authored. This manuscript will show trends in packaging and materials along with examples of emerging failure mechanisms that need to be understood to ensure reliability in highly integrated products.

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Processor-level reliability simulator for time-dependent gate dielectric breakdown

Chen

Liu

Cha

et al. 2015

Microprocessors and Microsystems

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Time-dependent gate dielectric breakdown (TDDB) is a leading reliability concern for modern microprocessors. In this paper, a framework is proposed to analyze the impact of TDDB on state-of-art microprocessors and to estimate microprocessor lifetimes due to TDDB. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we perform timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to TDDB and to estimate the lifetime distribution of logic blocks. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of TDDB degradation to estimate memory lifetime distributions. The lifetimes of memory blocks are then combined with the lifetimes of logic blocks to provide an estimate of the system lifetime distribution.

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Determination of CPU use conditions

Cited by 25 publications

References 5 publications

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Package reliability and performance trends in an era of product integration

Processor-level reliability simulator for time-dependent gate dielectric breakdown

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