Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack

Vaidyanathan, Kaushik; Das, Bishnu Prasad; Pileggi, Larry

doi:10.1145/2593069.2593123

Cited by 34 publications

(13 citation statements)

References 7 publications

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Section: A Destructive Vs Nondestructive Methodsmentioning

confidence: 99%

“…However, split manufacturing does not provide Trojan detection by itself. Destructive stress tests on selected back-end-of-line stacks can detect reliability attacks [48]. Trusted monitor chips stacked on top of an untrusted chip using through-silicon vias (TSVs) may be used to actively detect attacks [49] or selected wires may be lifted (using TSVs) to a secure layer to obfuscate a design [106].…”

Section: B Tpad Vs Other Techniquesmentioning

confidence: 99%

“…For example, Scanning Electron Microscopy (SEM) or Focused Ion Beam (FIB) [52] could be used to destructively delayer chips, and verify transistors and interconnects. Destructive stress tests may be used to detect reliability attacks (Appendix A) [48].However, this approach becomes difficult when Trojans are only inserted into a select few chips. For example, assume that if a chip containing a Trojan is destructively tested or inspected, the Trojan will be found and that particular chip will be destroyed.…”

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confidence: 99%

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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Ganesan

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both ASICs and FPGAs. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1. The area and power costs of our approach can range between 7.4-165% and 0.07-60%, respectively, depending on the design and the attacks targeted; 2. The speed impact can be minimal (close to 0%); 3. Our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4. Our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse-engineering). 5. Our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly. I. INTRODUCTION HERE is growing concern about the trustworthiness of integrated circuits (ICs). If an untrusted party fabricates an IC, there is potential for an adversary to insert a malicious hardware Trojan [1], an unauthorized modification of the IC resulting in incorrect functionality and/or sensitive data being exposed [2]. These include (but are not limited to) [3]: a) Modification of functional behavior through logic changes: Index TermsFor example, extra logic gates may be inserted to force an incorrect logic value on a wire at some (arbitrary) point in time (Fig. 1a) [2]. b) Electrical modification: For example, extra capacitive loading may be placed on a circuit path to alter timing characteristics of the IC (Fig. 1b) [2]. c) Reliability degradation: For example, aging of transistors (e.g., Negative Bias Temperature Instability (NBTI)) may be accelerated, degrading reliability ( Fig. 1c) [4]. A hardware Trojan is detected when we report malicious modifications to an IC. A hardware Trojan is prevented when Manuscript received January 9, 2015; revised May 8, 2015; accepted July 20, 2015. Work supported by IARPA Trusted Integrated Chips (TIC) Program. All authors are with Dept. of Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: tonyfwu@stanford.edu). S. Mitra is also with Dept. of Computer Science, Stanford University.we stop a hardware Trojan from being inserted. Part of the challenge in detecting or preventing hardware Trojans arises from the fact that...

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Section: A Destructive Vs Nondestructive Methodsmentioning

confidence: 99%

Section: B Tpad Vs Other Techniquesmentioning

confidence: 99%

mentioning

confidence: 99%

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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Ganesan

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…They applied their techniques in mult24and a5/1to present a statistical analysis of the performance yield when filling the standard cells in spared space in a complex digital design. The method of split manufacturing is further expanded to the application of reliable attack detection with test-only BEOL [14].…”

Section: Split Manufacturing In the Digital Domainmentioning

confidence: 99%

“…Even though the concept is straightforward, a successful implementation requires further research on various aspects, especially the balance between cost and security when the designer splits the layout into FEOL and BEOL. Analytical and experimental results have already been presented for digital circuits [8][9][10][11][12][13][14][15]. However, the analog/RF designs are rarely discussed when using split manufacturing, even though analog/RF circuits are more likely to be IP piracy victims than their digital counterparts.…”

Section: Introductionmentioning

confidence: 99%

Beyond the Interconnections: Split Manufacturing in RF Designs

Yuan

Jin

2015

Electronics

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With the globalization of the integrated circuit (IC) design flow of chip fabrication, intellectual property (IP) piracy is becoming the main security threat. While most of the protection methods are dedicated for digital circuits, we are trying to protect radio-frequency (RF) designs. For the first time, we applied the split manufacturing method in RF circuit protection. Three different implementation cases are introduced for security and design overhead tradeoffs, i.e., the removal of the top metal layer, the removal of the top two metal layers and the design obfuscation dedicated to RF circuits. We also developed a quantitative security evaluation method to measure the protection level of RF designs under split manufacturing. Finally, a simple Class AB power amplifier and a more sophisticated Class E power amplifier are used for the demonstration through which we prove that: (1) the removal of top metal layer or the top two metal layers can provide high-level protection for RF circuits with a lower request to domestic foundries; (2) the design obfuscation method provides the highest level of circuit protection, though at the cost of design overhead; and (3) split manufacturing may be more suitable for RF designs than for digital circuits, and it can effectively reduce IP piracy in untrusted off-shore foundries.

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