Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs

Duan, Yuelu; Feng, Xiaobing; Wang, Lei; Zhang, Chao; Yew, Pen-Chung

doi:10.1109/cgo.2009.29

Cited by 16 publications

(21 citation statements)

References 26 publications

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“…(Delay set analysis) Various compiler based approaches [11,12,18,22,34] have been proposed to minimize the number of fences required to enforce SC. These approaches are generally based on a technique called delay set analysis, developed by Shasha and Snir [32], which finds a minimal set of execution orderings that must be enforced to guarantee SC.…”

Section: Sequential Consistencymentioning

confidence: 99%

“…Likewise the memory fence added after the update of flag2 ensures that processor P2 stalls until this update completes. While this ensures SC, the insertion of such memory fences can significantly slowdown the program [11,12,18].…”

Section: Introductionmentioning

confidence: 98%

“…• Compared to previous software based approaches, our approach significantly reduces the slowdown. While the best known prior implementation causes an overhead of 45% [11] for the SPLASH-2 benchmarks, we reduce the overhead to only 12%. • Compared to previous hardware approaches towards SC which require speculation and its associated hardware costs, our approach does not require any speculation.…”

Section: Introductionmentioning

confidence: 98%

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Efficient Sequential Consistency Using Conditional Fences

Lin

Nagarajan

Gupta

2011

Int J Parallel Prog

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Among the various memory consistency models, the sequential consistency (SC) model is the most intuitive and enables programmers to reason about their parallel programs the best. Nevertheless, processor designers often choose to support relaxed memory consistency models because the weaker ordering constraints imposed by such models allow for more instructions to be reordered and enable higher performance. Programs running on machines supporting weaker consistency models can be transformed into ones in which SC is enforced. The compiler does this by computing a minimal set of memory access pairs whose ordering automatically guarantees SC. To ensure that these memory access pairs are not reordered, memory fences are inserted. Unfortunately, insertion of such memory fences can significantly slowdown the program. We observe that the ordering of the minimal set of memory accesses that the compiler strives to enforce, is typically already enforced in the normal course of program execution. A study we conducted on programs with compiler inserted memory fences shows that only 8% of the executed instances of the memory fences are really necessary to ensure SC. Motivated by this study we propose the conditional fence mechanism, known as C-Fence that utilizes compiler information to decide dynamically if there is a need to stall at each fence, only stalling when necessary. Our experiments with SPLASH-2 benchmarks show that, with C-Fences and a centralized 123 Int J Parallel Prog (2012) 40:84-117 85 active table, programs can be transformed to enforce SC incurring only 12% slowdown, as opposed to 43% slowdown using normal fence instructions. Our approach requires very little hardware support (<350 bytes of on-chip-storage) and it avoids the use of speculation and its associated costs. Furthermore, to ameliorate the contention in the centralized active table arising from the increasing number of processors, we also design a distributed active table, which further improves the performance of C-Fence for a larger number of processors.

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Section: Sequential Consistencymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 98%

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Efficient Sequential Consistency Using Conditional Fences

Lin

Nagarajan

Gupta

2011

Int J Parallel Prog

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“…Lin et al [20] can hide some of the resulting fence delay with architectural support. Duan et al [12] use a race detector to construct a graph of races dynamically. Then, off-line, they traverse the graph to find potential SCVs.…”

Section: Other Related Workmentioning

confidence: 99%

“…Other researchers have used the compiler to identify race pairs that could cause SCVs, typically using the Delay Set algorithm, and then insert fences to prevent cycles [12,14,17,19,31]. Since the compiler has limited information, these approaches tend to be very conservative and result in substantial slowdowns.…”

Section: Introductionmentioning

confidence: 99%

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Muzahid

Torrellas

2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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Past work has focused on detecting data races as proxies for Sequential Consistency (SC) violations. However, most data races do not violate SC. In addition, lock-free data structures and synchronization libraries sometimes explicitly employ data races but rely on SC semantics for correctness. Consequently, to uncover SC violations, we need to develop a more precise technique.This paper presents Vulcan, the first hardware scheme to precisely detect SC violations at runtime, in programs running on a relaxed-consistency machine. The scheme leverages cache coherence protocol transactions to dynamically detect cycles in memoryaccess orders across threads. When one such cycle is about to occur, an exception is triggered. For the conditions considered in this paper and with enough hardware, Vulcan suffers neither false positives nor false negatives. In addition, Vulcan induces negligible execution overhead, requires no help from the software, and only takes as input the program executable. Experimental results show that Vulcan detects three new SC violation bugs in the Pthread and Crypt libraries, and in the fmm code from SPLASH-2. Moreover, Vulcan's negligible execution overhead makes it suitable for on-the-fly use.

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