Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Muzahid, Abdullah; Qi, Shanxiang; Torrellas, Josep

doi:10.1109/micro.2012.41

Cited by 30 publications

(26 citation statements)

References 31 publications

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“…Section 2 provides an indepth comparison of SOFRITAS with other strong memory consistency models, and we describe SOFRITAS's relationship with other relevant work here. Several schemes have been proposed for detecting sequential-consistency violations with custom hardware support [18,39,42]. These schemes detect a cycle of data races, which indicates that SC has been compromised, and use speculation to rollback execution to before the SC violation occurred.…”

Section: Related Workmentioning

confidence: 99%

Sofritas

DeLozier

Eizenberg

Lucia

et al. 2018

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Syste

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Correctly synchronizing multithreaded programs is challenging and errors can lead to program failures such as atomicity violations. Existing strong memory consistency models rule out some possible failures, but are limited by depending on programmer-defined locking code. We present the new Ordering-Free Region (OFR) serializability consistency model that ensures atomicity for OFRs, which are spans of dynamic instructions between consecutive ordering constructs (e.g., barriers), without breaking atomicity at lock operations. Our platform, Serializable Ordering-Free Regions for Increasing Thread Atomicity Scalably (SOFRITAS), ensures a C/C++ program's execution is equivalent to a serialization of OFRs by default. We build two systems that realize the SOFRI-TAS idea: a concurrency bug finding tool for testing called SofriTest, and a production runtime system called SoPro.SofriTest uses OFRs to find concurrency bugs, including a multi-critical-section atomicity violation in memcached that weaker consistency models will miss. If OFRs are too coarse-grained, SofriTest suggests refinement annotations automatically. Our software-only SoPro implementation has high performance, scales well with increased parallelism, and prevents failures despite bugs in locking code. SoPro has an average overhead of just 1.59x on a single-threaded execution and 1.51x on sixteen threads, despite pthreads' much weaker memory model.

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Section: Related Workmentioning

confidence: 99%

Sofritas

DeLozier

Eizenberg

Lucia

et al. 2018

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Syste

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“…Hardware support for MCM verification: An alternative approach to ensure correctness, is fault-tolerance via hardware support for detecting MCM violations dynamically [54,55,56,57], and recovering from them. Our proposal, which focusses on test generation, is orthogonal to these works.…”

Section: Related Workmentioning

confidence: 99%

McVerSi: A test generation framework for fast memory consistency verification in simulation

Nagarajan

Elver

2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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The memory consistency model (MCM), which formally specifies the behaviour of the memory system, is used by programmers to reason about parallel programs. It is imperative that hardware adheres to the promised MCM. For this reason, hardware designs must be verified against the specified MCM. One common way to do this is via executing tests, where specific threads of instruction sequences are generated and their executions are checked for adherence to the MCM. It would be extremely beneficial to execute such tests under simulation, i.e. when the functional design implementation of the hardware is being prototyped. Most prior verification methodologies, however, target post-silicon environments, which when applied under simulation would be too slow.We propose McVerSi, a test generation framework for fast MCM verification of a full-system design implementation under simulation. Our primary contribution is a Genetic Programming (GP) based approach to MCM test generation, which relies on a novel crossover function that prioritizes memory operations contributing to non-determinism, thereby increasing the probability of uncovering MCM bugs. To guide tests towards exercising as much logic as possible, the simulator's reported coverage is used as the fitness function. Furthermore, we increase test throughput by making the test workload simulation-aware. We evaluate our proposed framework using the Gem5 cycle accurate simulator in full-system mode with Ruby. We discover 2 new bugs due to the faulty interaction of the pipeline and the cache coherence protocol. Crucially, these bugs would not have been discovered through individual verification of the pipeline or the coherence protocol. We study 11 bugs in total. Our GP-based test generation approach finds all bugs consistently, therefore providing much higher guarantees compared to alternative approaches (pseudo-random test generation and litmus tests).

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“…It detects all races but has high overhead. The worked that followed improved performance by allowing for some races while ensuring that executions are sequentially consistent (SC) [37,55,43,51], or (stronger) region serializable (RS) [33,47]. These properties also simplify reasoning about racy executions but, in contrast to simple hardware support for CLEAN, guaranteeing them requires spare processors, the use of large dedicated hardware structures, or modifying the cache or the coherence protocol.…”

Section: Related Workmentioning

confidence: 99%

C lean

Segulja

Abdelrahman

2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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Data races make parallel programs hard to understand. Precise race detection that stops an execution on first occurrence of a race addresses this problem, but it comes with significant overhead. In this work, we exploit the insight that precisely detecting only write-after-write (WAW) and read-afterwrite (RAW) races suffices to provide cleaner semantics for racy programs. We demonstrate that stopping an execution only when these races occur ensures that synchronizationfree-regions appear to be executed in isolation and that their writes appear atomic. Additionally, the undetected racy executions can be given certain deterministic guarantees with efficient mechanisms.We present CLEAN, a system that precisely detects WAW and RAW races and deterministically orders synchronization. We demonstrate that the combination of these two relatively inexpensive mechanisms provides cleaner semantics for racy programs. We evaluate both software-only and hardware-supported CLEAN. The software-only CLEAN runs all Pthread benchmarks from the SPLASH-2 and PARSEC suites with an average 7.8x slowdown. The overhead of precise WAW and RAW detection (5.8x) constitutes the majority of this slowdown. Simple hardware extensions reduce the slowdown of CLEAN's race detection to on average 10.4% and never more than 46.7%.

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Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Cited by 30 publications

References 31 publications

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McVerSi: A test generation framework for fast memory consistency verification in simulation

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