“…However, SG‐MOSFETs with higher voltage ratings (e.g. ≥100 V) require deeper trenches, inducing a near‐linear increase in output capacitance ( C oss = C DS + C GD ) and R ON [6]. Consequently, it becomes increasingly crucial to improve the [ R ON × Q G ] figure‐of‐merit (FOM) for devices with medium‐ and high‐voltage ratings.…”
Section: Introductionmentioning
confidence: 99%
“…Although it is a common method to form a p ‐type region beneath the trench to alleviate the electric field in the blocking state [6, 11], it also brings the following issues: The out diffusion of the p ‐type region narrows the current path between two adjacent trenches and increases the static R ON , especially for MOSFETs with high channel density [11]. During turn‐on transients, the depleted p ‐type region cannot recover to neutral state immediately, causing a degradation in the dynamic output stored charge ( Q oss ) [6] and R ON [12–14]. Grounding the p ‐type region to the source contact can avoid this degradation [12], but the increased static R ON remains a problem.…”
Section: Introductionmentioning
confidence: 99%
“…Although it is a common method to form a p-type region beneath the trench to alleviate the electric field in the blocking state [6,11], it also brings the following issues:…”
Section: Introductionmentioning
confidence: 99%
“…2. During turn-on transients, the depleted p-type region cannot recover to neutral state immediately, causing a degradation in the dynamic output stored charge (Q oss ) [6] and R ON [12][13][14]. Grounding the p-type region to the source contact can avoid this degradation [12], but the increased static R ON remains a problem.…”
A 100‐V Taper‐Shielded trench Gate (TSG) power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with superior figure‐of‐merit (FOM) is proposed and investigated in this paper. The gate of the proposed TSG‐MOSFET has a tapered shape to reduce the gate‐to‐drain overlap capacitance (CGD) and the gate charge (QG). The vertical drift region doping profile of the proposed TSG‐MOSFET is enhanced in two ways. First is to use a multi‐step epitaxial growth to produce a non‐uniform doping profile. Second is to place a lightly doped n‐region at the trench bottom. The bulk electric field in the blocking state can be more evenly distributed, allowing a shorter drift region and lower specific ON‐resistance (RON,sp). Both technology computer‐aided design (TCAD) simulations and experiments were performed to evaluate the proposed device. The proposed device exhibits an improved RON,sp of 27 mΩ·mm2 with a breakdown voltage (BV) of 105 V. The third quadrant performance and the reverse recovery characteristics are also greatly improved. During reverse conduction, the amount of the excessive carriers stored in the drift region is reduced due to the shortened drift region and optimized drift region doping profile. The reverse recovery charge (Qrr) is decreased from 70 to 49 nC. When compared to its state‐of‐the‐art counterparts, the measured [RON × QG] FOM and the Qrr showed a reduction of 23% and 28%, respectively.
“…However, SG‐MOSFETs with higher voltage ratings (e.g. ≥100 V) require deeper trenches, inducing a near‐linear increase in output capacitance ( C oss = C DS + C GD ) and R ON [6]. Consequently, it becomes increasingly crucial to improve the [ R ON × Q G ] figure‐of‐merit (FOM) for devices with medium‐ and high‐voltage ratings.…”
Section: Introductionmentioning
confidence: 99%
“…Although it is a common method to form a p ‐type region beneath the trench to alleviate the electric field in the blocking state [6, 11], it also brings the following issues: The out diffusion of the p ‐type region narrows the current path between two adjacent trenches and increases the static R ON , especially for MOSFETs with high channel density [11]. During turn‐on transients, the depleted p ‐type region cannot recover to neutral state immediately, causing a degradation in the dynamic output stored charge ( Q oss ) [6] and R ON [12–14]. Grounding the p ‐type region to the source contact can avoid this degradation [12], but the increased static R ON remains a problem.…”
Section: Introductionmentioning
confidence: 99%
“…Although it is a common method to form a p-type region beneath the trench to alleviate the electric field in the blocking state [6,11], it also brings the following issues:…”
Section: Introductionmentioning
confidence: 99%
“…2. During turn-on transients, the depleted p-type region cannot recover to neutral state immediately, causing a degradation in the dynamic output stored charge (Q oss ) [6] and R ON [12][13][14]. Grounding the p-type region to the source contact can avoid this degradation [12], but the increased static R ON remains a problem.…”
A 100‐V Taper‐Shielded trench Gate (TSG) power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with superior figure‐of‐merit (FOM) is proposed and investigated in this paper. The gate of the proposed TSG‐MOSFET has a tapered shape to reduce the gate‐to‐drain overlap capacitance (CGD) and the gate charge (QG). The vertical drift region doping profile of the proposed TSG‐MOSFET is enhanced in two ways. First is to use a multi‐step epitaxial growth to produce a non‐uniform doping profile. Second is to place a lightly doped n‐region at the trench bottom. The bulk electric field in the blocking state can be more evenly distributed, allowing a shorter drift region and lower specific ON‐resistance (RON,sp). Both technology computer‐aided design (TCAD) simulations and experiments were performed to evaluate the proposed device. The proposed device exhibits an improved RON,sp of 27 mΩ·mm2 with a breakdown voltage (BV) of 105 V. The third quadrant performance and the reverse recovery characteristics are also greatly improved. During reverse conduction, the amount of the excessive carriers stored in the drift region is reduced due to the shortened drift region and optimized drift region doping profile. The reverse recovery charge (Qrr) is decreased from 70 to 49 nC. When compared to its state‐of‐the‐art counterparts, the measured [RON × QG] FOM and the Qrr showed a reduction of 23% and 28%, respectively.
“…[10][11][12] Orouji et al [13] studied the unique features that were exhibited by power in the 4H-SiC UMOSFET, where the n-and p-type columns in the drift region were incorporated in order to improve the breakdown voltage, on-resistance. In order to achieve lower on-resistance and better switching performance, Deng et al [14] investigated a device structure that had a built-in floating component. In order to optimize the trade-off between on-resistance and short circuit ruggedness, He et al [15] improved a 4H-SiC super-junction trench MOSFET by adding a grounded p+buried layer below the p-body, an oxide trench under the gate, and a p-region surrounding the oxide trench.…”
This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance (R
on,sp). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field (E-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that R
on,sp of the modified structure, and breakdown voltage (V
BR) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit (
FOM
=
V
BR
2
/
R
on
,
sp
) is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge (Q
gd) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the V
BR of the device without degradation of dynamic performance.
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