2017
DOI: 10.3390/jlpea7030023
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DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Abstract: Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and… Show more

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Cited by 55 publications
(26 citation statements)
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References 59 publications
(120 reference statements)
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“…In this section, we describe the organization of the memristor crossbar of our FSC driver and the peripheral circuitry. Figure 7 illustrates the internal structure of the memristor crossbar array that is used to design the crossbar array of the proposed driver, which is adapted from the memory array organization of representative non-volatile memory simulators, i.e., NVSim [31] and Destiny [32]. The crossbar array features eight banks in the SLC ReRAM-based design; each bank is hierarchically organized into mats and sub-arrays.…”
Section: Hardware Implementationmentioning
confidence: 99%
“…In this section, we describe the organization of the memristor crossbar of our FSC driver and the peripheral circuitry. Figure 7 illustrates the internal structure of the memristor crossbar array that is used to design the crossbar array of the proposed driver, which is adapted from the memory array organization of representative non-volatile memory simulators, i.e., NVSim [31] and Destiny [32]. The crossbar array features eight banks in the SLC ReRAM-based design; each bank is hierarchically organized into mats and sub-arrays.…”
Section: Hardware Implementationmentioning
confidence: 99%
“…Challenges in Achieving High Accuracy and Performance: Compared to SRAM, ReRAM has high write energy/latency which increases the overall power consumption [39,40]. ReRAM limitations, e.g., series line resistance and sneak-path, further reduce the performance [41].…”
Section: Challenges In Using Rerammentioning
confidence: 99%
“…Table 4 compares the properties Figure 3). Once SLC wears, future writes are redirected to MLC, which harms performance MLC (+) improves density and lowers cost (−) lowers lifetime due to small write endurance of MLC DRAM or SCM (+) improves performance and lifetime; bridges speed gap between memory and storage 29 ; allows performing reads/writes in near-constant time regardless of the location of data inside memory. SCMs do not require erase operations and have much higher endurance than Flash memory.…”
Section: Mapping Techniquesmentioning
confidence: 99%