DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling

Abstract

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26× to 4× with respect to other parallel state-of-the art DSE techniques.

Sherlock: A Multi-Objective Design Space Exploration Framework

“…This enables the rapid exploration of the design space by sampling more potential solutions. DeSpErate++ [11] uses a scheduling system to predict and eiciently simulate the designs and quickly explores the design space of the analytical model. Another approach builds compute and memory models based on the compiler internal representation that can be used as surrogate models to signiicantly speed up the DSE process [30,31].…”

Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors

“…As shown in Figure 1, STS consists of a main tuning loop that constructs synthesis scenarios consisting of synthesis parameter settings (Step (1)), submits and monitors synthesis jobs (2-3), analyzes the results (4), and iteratively refines the solutions (5). A second background loop archives the results of all runs from all macros, users, and projects.…”

“…The general goal of STSS is to take a list of STS-run requests and optimally determine the order in which to submit them to the queue manager, given resource limits. The more general problem STSS addresses is CAD-tool scheduling, which recently is receiving more attention, e.g., for scheduling architectural simulations for a single design [5]. The process begins at Step (1) in Figure 7 where the following inputs are provided to STSS: A) a list of STS run requests and a reference set of synthesis QoR stats for the multiple macros (note that if the reference QoR stats are not available, STSS will first schedule one synthesis run on all macros in the list to generate them), B) a priority-ranking policy and global cost function, which will be described below, and C) compute resource limits.…”