Designing systems-on-chip using cores

Abstract

Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increasingly relying on reuse of intellectual property (IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. That is the goal, in theory. In practice, assembling an SoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discusses the main challenges in SoC designs using IP blocks and elaborates on the methodology and tools being put in place at IBM for addressing the problem. It explains IBM's SoC architecture and gives algorithmic details on the high-level tools being developed for SoC design.

Software Programmable ADC and DAC interfaces in VHDL

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Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications

“…In order to reduce design costs and time-to-market, systems are built by assembling pre-designed functional modules (processors, memory, dedicated hardware blocks), called IP (Intellectual Property) cores [1]. They can be reused from previous designs or acquired from third-party vendors.…”

VCore-based design methodology

“…But the cited research works have not yet established, or considered the re-use of design components at a high level design abstraction. Although there is a research work [6] on the re-use at the architecture level, the re-use at the system level design will be a major research issue towards the era of 65nm process technology, when a SoC will have more than 100 million transistors.…”