2009 IEEE LEOS Annual Meeting Conference Proceedings 2009
DOI: 10.1109/leos.2009.5343493
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Designing manycore processor networks using silicon photonics

Abstract: We present a vertical integration approach for designing silicon photonic networks for communication in manycore systems. Using a top-down approach we project the photonic device requirements for a 64-tile system designed in 22 nm technology.

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Cited by 1 publication
(2 citation statements)
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“…Consider the R-OWN communication shown in Figure 2. For example, core (0, 0, 0) and core (0, 7, 2) both want to send packets to core (1,7,3), and router (0, 3) (H0) possess the adaptive wireless link of cluster 0. In other words, adaptive wireless link-F0 is connected to cluster 1 at this point of time.…”
Section: Routing Mechanism Of 256-core R-ownmentioning
confidence: 99%
See 1 more Smart Citation
“…Consider the R-OWN communication shown in Figure 2. For example, core (0, 0, 0) and core (0, 7, 2) both want to send packets to core (1,7,3), and router (0, 3) (H0) possess the adaptive wireless link of cluster 0. In other words, adaptive wireless link-F0 is connected to cluster 1 at this point of time.…”
Section: Routing Mechanism Of 256-core R-ownmentioning
confidence: 99%
“…Optical interconnects o↵er several advantages such as low energy consumption (⇠0.25pJ/bit), reduced link latency (⇠ps), and increased bandwidth (⇠40Gbps) via wavelength division multiplexing (WDM)-all of which makes optics a suitable technology for on-chip communications [17], [14], [7], [3]. However, for large core counts, crossbar-based architectures such as Corona [17], Firefly [14], and 3D-NoC [12] su↵er from scalability issues because the number of ring modulators and photodetectors increase quadratically with the number of cores, thus resulting in high area and power overhead.…”
Section: Introductionmentioning
confidence: 99%