Designing circuits with partial scan

Agrawal, Vishwani D.; Cheng, Kwang-Ting; Johnson, D.D.; Lin, Tonysheng

doi:10.1109/54.2032

Cited by 106 publications

(12 citation statements)

References 3 publications

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“…Agrawal et al selected a near optimal subset of scan flip-flops [20]. The method tried to achieve a required test coverage with minimum overhead through the use of a modified path-oriented decision making (PODEM) automatic test pattern generation program [21].…”

Section: B Partial-scan and Dftmentioning

confidence: 99%

SPARTAN: a spectral and information theoretic approach to partial-scan

Khan

Bushnell

Devanathan

et al. 2007

2007 IEEE International Test Conference

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Section: B Partial-scan and Dftmentioning

confidence: 99%

SPARTAN: a spectral and information theoretic approach to partial-scan

Khan

Bushnell

Devanathan

et al. 2007

2007 IEEE International Test Conference

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“…Early attempts at purely combinational ATPG-based partial scan design produced overheads that were often close to those of full-scan [2]. A low overhead partial-scan technique, in which scan flip-flops (FFs) break feedback paths, was proposed by Cheng and Agrawal [5], and Kunzmann and Wunderlich [25].…”

Section: Introductionmentioning

confidence: 99%

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does not allow the use of available combinational ATPG programs. The first contribution of this work is a combinational single-fault ATPG method for the most general class of acyclic sequential circuits. Without inserting any real hardware, we create a functionally equivalent "balanced" ATPG model of the circuit in which all reconverging paths have the same sequential depth. Some primary inputs and gates are duplicated in this model, which is converted into a combinational circuit by shorting all flip-flops. A test vector obtained by a combinational ATPG program for a fault in this combinational circuit is transformed into a test sequence to detect a corresponding fault in the original sequential circuit. A combinational ATPG program finds tests for all but a small set of faults that must be explicitly detected as multiple-faults. Those are modeled for ATPG using the second contribution of this work, which is a generalized method to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most + 3 modeling gates for a fault of multiplicity . We show that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. Benchmark results show at least an order of magnitude saving in the ATPG CPU time by the new combinational method over sequential ATPG.Index Terms-Acyclic sequential circuit, automatic test pattern generation (ATPG), balanced model, combinational test generation, design for test (DFT), partial scan, test.

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“…Careful ordering of the scan chain elements can reduce the interconnect or testing time [2] [3] [4] [5]. By giving up some of the controllability and observability of a fully scanned design, partial-scan designs [6] [7] [8] [9] [10] attempt to reduce the overhead by making only a subset of the system bistables scannable.…”

Section: Introductionmentioning

confidence: 99%