Designing applications for heterogeneous many-core architectures with the FlexTiles Platform

Janßen, Benedikt; Schwiegelshohn, Fynn; Koedam, Martijn; Duhem, François; Masing, Leonard; Werner, Stephan; Huriaux, Christophe; Courtay, Antoine; Wheatley, Emilie; Goossens, Kees; Lemonnier, Fabrice; Millet, Philippe; Becker, J.; Sentieys, Olivier; Hübner, Michael

doi:10.1109/samos.2015.7363683

Cited by 9 publications

(2 citation statements)

References 13 publications

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“…The future evolution of COTS components in deep scaled technologies (also for IoT) is moving toward multi-core system-on-chip where different macrocells (e.g., processors, memories) are integrated on-chip interconnected through a network on chip [102][103][104][105][106] and/or to application specific processors for sensor conditioning [107][108][109][110]. In such cases, the voltage level requirements will remain more or less the same.…”

Section: Dc/dc Architecture and Circuit-level Designmentioning

confidence: 99%

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

Gutiérrez¹

2017

Electronics

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Abstract:The paper presents a fully-integrated and universal DC/DC converter to minimize cost and size of power supply systems in wireless nodes for Internet-of-Things (IoT) applications. The proposed converter avoids the use of inductors and is made by a cascade of switching capacitor stages, implementing both step-down and step-up converting ratios, which regulate input sources from 1 V to 60 V to a voltage of about 4 V. Multiple linear regulators are placed at the end of the cascade to provide multiple and stable output voltages for loads such as memories, sensors, processors, wireless transceivers. The multi-output power converter has been integrated in a Bipolar-CMOS-DMOS (BCD) 180 nm technology. As case study, the generation of 3 output voltages has been considered (3 V, 2.7 V, and 1.65 V with load current requirements of 0.3 A, 0.3 A, and 0.12 A, respectively). Thanks to the adoption of a high switching frequency, up to 5 MHz, the only needed passive components are flying capacitors, whose size is below 10 nF, and buffer capacitors, whose size is below 100 nF. These capacitors can be integrated on top of the chip die, creating a 3D structure. This way, the size of the power management unit for IoT and CPS nodes is limited at 18 mm 2 . The proposed converter can also be used with changing input power sources, like power harvesting systems and/or very disturbed power supplies.

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Section: Dc/dc Architecture and Circuit-level Designmentioning

confidence: 99%

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

Gutiérrez¹

2017

Electronics

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“…Consequently, several research approaches have been proposed for adaptive and self-aware many-core systems to allow the re-usability and reconfigurability of many-core architectures to be adjusted according to multiple requirements for different application domains [8], [9]. As a result, an expected reduction in development time and cost can be achieved by the adoption of adaptive many-core approaches.…”

Section: Introductionmentioning

confidence: 99%

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Kamaleldin¹,

Göhringer²

2022

IEEE Access

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Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of opensource RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Intertile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8x32-bit tiles and 316 MOPS for 8x64-bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex Ultrascale+ FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

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A Dynamic Partial Reconfigurable Overlay Framework for Python

Janßen

Kastner

Wingender

et al. 2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Designing applications for heterogeneous many-core architectures with the FlexTiles Platform

Cited by 9 publications

References 13 publications

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

A Dynamic Partial Reconfigurable Overlay Framework for Python

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