Designing an asynchronous microcontroller using Pipefitter

Blunno, I.; Lavagno, Luciano

doi:10.1109/iccd.2002.1106818

Cited by 4 publications

(6 citation statements)

References 16 publications

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“…To validate the efficacy of the proposed approach, the error detector implemented by the proposed approach is compared with those implemented by desynchronization (specifically, the method reported in [80]) and Pipefitter [64].…”

Section: Comparisons With Other Methodsmentioning

confidence: 99%

“…Another way of synthesizing asynchronous systems is the asynchronous logic synthesis approach [64] [65] [89] [90]. In this approach, a high-level description of the design is partitioned into its control and datapath components.…”

Section: Logic Synthesis Approachmentioning

confidence: 99%

“…In particular, the synthesis of an STG into a circuit requires enumerating the STG's entire state space (the state space explosion problem) and uniquely encoding every reachable state of the controller (the complete state coding problem [91]). Thus, for large STGs, the synthesis time can be prohibitively long [64] [89] [92]. While a work-around to this problem is to partition a complex circuit into several parts and synthesize them separately, no tools are currently available to perform the partitioning automatically.…”

Section: Logic Synthesis Approachmentioning

confidence: 99%

“…Control resynthesis involves grouping interconnected handshake components into blocks, composing the behavior of each block into a graph-based specification, such as an STG or a burst-mode specification, and resynthesizing the specification into a monolithic control component [66] [123]). This means that even for advanced synthesis tools, such as Petrify [43], the time taken to synthesize large circuits may be prohibitively long [64] [92]. Another problem with control resynthesis is that the steps involved for composing the block specification are computationally expensive [66].…”

Section: Control Resynthesismentioning

confidence: 99%

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Design methodologies for low-power asynchronous-logic digital systems

Law¹

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Asynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks. Three main contributions are made in this thesis to the design of asynchronous pipelines with low asynchronous control overheads. First, a synthesis method for asynchronous pipelines is proposed that adopts a coarse-grain approach to the synthesis of asynchronous control networks, thereby leading to low asynchronous control overhead pipelines. It also has the advantages of offering a largely transparent modeling style for asynchronous communication and ease for integration into the conventional synchronous design flow. The efficacy of the proposed synthesis method is demonstrated through the design of a Reed-Solomon error detector and an interpolated finite-impulse-response filterbank-the simulated circuit implementations based on the proposed synthesis method dissipate on the average 31% less energy than those implemented by comparable reported synthesis methods. Second, two optimization methods are proposed for reducing the circuit area and power dissipation of asynchronous control networks while satisfying pipeline throughput constraints. The first proposed optimization method-handshake component fusion-is a form of peephole optimization that iteratively selects a pair of handshake components that share input channel sources or output channel destinations and replaces them with a single component. The second proposed optimization method-optimal decoupling-searches for the optimal mix of handshake components of different degree of concurrency in a given asynchronous control network with the objective of incurring the least circuit area and power dissipation for the control network, while satisfying a throughput constraint. The proposed optimization methods are applied on three designs and are found to reduce the asynchronous control networks' transistor count and energy dissipation by, on the average, 28% and 36%, respectively. A fundamental requirement of the proposed optimization methods is that the minimal-support S-invariants for the Petri net models of the asynchronous control networks are recomputed at each optimization iteration. vii ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Arising from the fundamental requirement mentioned above, the third main contribution of the thesis is a fast and memory-efficient algorithm for computing all minimal-support S-invariants for ordinary Petri nets. Based on a large number of test problems, the proposed algorithm is demonstrated to be at least 2.2x faster and 1.8x more memory efficient than reported algorithms. The proposed synthesis method, ...

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Section: Comparisons With Other Methodsmentioning

confidence: 99%

Section: Logic Synthesis Approachmentioning

confidence: 99%

Section: Logic Synthesis Approachmentioning

confidence: 99%

Section: Control Resynthesismentioning

confidence: 99%

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Design methodologies for low-power asynchronous-logic digital systems

Law¹

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“…Employing existing HDL language to specify async circuits from the system level not only mask the complexity of systems, but also enable off-the-shelf commercial EDA tools to verify functionality, which is definitely a promising interface with current sync design flow. Thereafter, system specifications are specified in high level abstraction, and some tools, for example, Pipefitter [66], are reported to transform high level system specification into graph-based specification, and existing graph synthesis tools, such…”

Section: Logic Synthesismentioning

confidence: 99%

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Zhou¹

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In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital circuits and systems based on sync approach is becoming more challenging due to the increase in process, voltage and temperature (PVT) variations in the deep submicron fabrication process. An alternative design approach which is based on the asynchronous-logic (async), is

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