Designing a runtime reconfigurable processor for general purpose applications

Abstract

A superscalar microprocessor with a variable number of execution units which are dynamically configured during program execution has been modeled. The runtime behaviour of an executed application is determined using a Trace Cache and the most suitable hardware configuration is loaded dynamically. This paper discusses major design aspects of the ongoing implementation process based on a partial reconfiguration design flow. Thus, some microarchitectural components are put together to form a fixed module while different sets of execution units build up reconfigurable ones. The communication between fixed and reconfigurable modules is assured by Xilinx Bus Macros.

Trusted computing - A new challenge for embedded systems

“…In [16], it is shown that the reconfigurable coprocessor speeds up the architecture by 190 for a specific application (EEMBC). A similar approach is proposed in [17] where the authors define a complete reconfigurable core for the processor. The instruction set of the architecture is fixed but the core of the processor has different configurations for the ALU.…”

Dynamic configuration steering for a reconfigurable superscalar processor

“…With these definitions, the number of unique combinations is equal to the number of nonnegative integer solutions to Equation (1), which is expressed in component form in Equation (2). As stated earlier, we assume a minimal RFU size of unity, which implies that all combinations are complete in the sense that "wasted space," does not exist.…”

“…The architecture assumed in this paper is similar to that presented in [1] and originally proposed in [2]. This architecture is partially run-time reconfigurable at the level of reconfigurable functional unit (RFU) "slots".…”

“…Each type of execution unit that can be loaded requires one or more RFU slots. Five types of execution units are included: (1) integer arithmetic/logic units (IntALUs), (2) integer multiply/divide units (Int-MDUs), (3) load-store units (LSUs), (4) floating-point arithmetic/logic units (FP-ALUs), and (5) floating-point multiply/divide units (FP-MDUs) [1]. Table 1 lists the number of slots required to support each type of execution unit.…”