Designing a high-throughput VLC decoder. I. Parallel decoding methods

Lin, Hong-Da; Messerschmitt, David G.

doi:10.1109/76.143419

Cited by 42 publications

(17 citation statements)

References 17 publications

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“…{LOC [5], T [5], C [5]} are accessed from the memory module 1 and stored in registers, {pMDR, T , C }. According to the bit_stream [2 : 3] , the prediction branch model is the set 00 of LOC [5] in pMDR.…”

Section: Decoding Procedures With Codeword Boundary Predictionmentioning

confidence: 99%

“…With the bit_stream[0 : 1], the codeword cannot be decoded, nor can the codeword length be predicted. Based on the set 00 of LOC [5], the bit_stream [2 : 3] is in both ACT and S conditions. After comparing the bit_stream [4 : 5] with the prediction branch model, it is found that the codeword is the special terminal-node and one single bit, 1, remains to be decoded after the bit_stream [2 : 3].…”

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

“…2.2) Because the codeword has not been decoded, it is essential to find the decoding information of the next cycle. The address of the next required {LOC, T, C} is expressed by (C[5] 7) (OFSC 1) 8, where the OFSC is the number of nonterminal nodes before the set 00 of LOC [5] in pMDR. But this address 8 is greater than , {R [2], T [2]} instead of {LOC [8], T [8], C [8]} are accessed from the memory module 2, where the new address 2 is the result of ( ).…”

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

“…1.1) LOC [5], T [5] in pMDR, T are shifted into dMDR, T . 1.2) R[2], T [2] are loaded into pMDR, T .…”

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

“…1.2) R[2], T [2] are loaded into pMDR, T . 2.1) The branch model set 00 of LOC [5] in dMDR is used for decoding the bit_stream [2 : 3] which is not the terminal-node. The codeword length needs not be predicted since it has been known in the previous cycle.…”

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

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A high-throughput memory-based VLC decoder with codeword boundary prediction

Shieh

Lee²,

Lee³

2000

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-In this paper, we present a high-throughput memorybased VLC decoder with codeword boundary prediction. The required information for prediction is added to the proposed branch models. Based on an efficient scheme, these branch models and the Huffman tree structure are mapped onto memory modules. Taking the prediction information, the decompression scheme can determine the codeword length before the decoding procedure is completed. Therefore, a parallel-processor architecture can be applied to the VLC decoder to enhance the system performance. With a clock rate of 100 MHz, a dual-processor decoding process can achieve decompression rate up to 72.5 Msymbols/s on the average. Consequently, the proposed VLC decompression scheme meets the requirements of current and advanced multimedia applications.

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Section: Decoding Procedures With Codeword Boundary Predictionmentioning

confidence: 99%

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

“…1.1) LOC [5], T [5] in pMDR, T are shifted into dMDR, T . 1.2) R[2], T [2] are loaded into pMDR, T .…”

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

Section: 1) Neither Terminal-nodes Nor Prediction Messagesmentioning

confidence: 99%

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A high-throughput memory-based VLC decoder with codeword boundary prediction

Shieh

Lee²,

Lee³

2000

IEEE Trans. Circuits Syst. Video Technol.

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Entropy CODEC from behavioral description based LSI-CAD for fully programmable image coding system

Suzuki

Ono

1996

Des Autom Embed Syst

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Entropy coding, as used for lossless compression in image coding, is dominated by serial bit processing on variable wordlength data. Digital signal processors (DSPs), in which pipeline processors play a central role, fail to yield adequate performance for this kind of application. This paper proposes a new approach that fulfills the two requirements for bit processing, the dominant task in entropy coding: high-performance and functional flexibility.This approach is based on Amphibious logic combining a high-level design LSI-CAD system with a functionally reconfigurable Field Programmable Gate Array (FPGA). Functions are programmed via a behavioral description program in a high-level design LSI-CAD system. In order to show the effectiveness of the newly proposed Amphibious logic approach, we designed JPEG-type Huffman and arithmetic CODECs for encoding still images. A comparison with the results of the processing speeds of DSPs and general-purpose microprocessors proves that the Amphibious logic is indeed possible to attain the dual goals of high performance and programmability. The proposed approach can be used to augment a conventional DSP by allocating the functions of numerical processing and bit stream processing, as used in image coding algorithms, between DSPs and FPGAs.

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