1996
DOI: 10.1109/4.509848
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Design techniques for silicon compiler implementations of high-speed FIR digital filters

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Cited by 71 publications
(27 citation statements)
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“…While not formally required, it is often preferred to select the filter order, N , to be an integer multiple of the decimation factors, D. Finally, it should be noted that for even D there are two different ways to decimate an even-order impulse response to obtain a linear-phase filter [10]. To the best of the authors' knowledge, this has not been considered in any of the previous works on coefficient decimation filters.…”
Section: Coefficient Decimation Reviewmentioning
confidence: 86%
“…While not formally required, it is often preferred to select the filter order, N , to be an integer multiple of the decimation factors, D. Finally, it should be noted that for even D there are two different ways to decimate an even-order impulse response to obtain a linear-phase filter [10]. To the best of the authors' knowledge, this has not been considered in any of the previous works on coefficient decimation filters.…”
Section: Coefficient Decimation Reviewmentioning
confidence: 86%
“…The impulse response of a linear phase FIR is either symmetrical or antisymmetrical. Design techniques of FIR filters have been well studied for ASIC implementations [7]. In this paper, we present the general interpolation FIR architecture specifically optimized for FPGAs.…”
Section: Multi-stage Upsampling Filtersmentioning
confidence: 99%
“…Efficient FIR implementations take advantage of the filter coefficients symmetry to minimize the number of multiplications. It has been shown that when the interpolation ratio is even and the length of the FIR filter is odd, we can have two linear phase subfilters after decomposing into polyphase structure [7]. Therefore we choose the interpolation ratios to be two for all of the interpolation filters, while designing them to have odd number of taps.…”
Section: Multi-stage Upsampling Filtersmentioning
confidence: 99%
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