Design space exploration on the H.264 4/spl times/4 Hadamard transform

Porto, Marcelo; Silva, T.L. da; Porto, Roger; Agostini, Luciano; Silva, I.V. da; Bampi, Sérgio

doi:10.1109/norchp.2005.1597021

Cited by 8 publications

(8 citation statements)

References 5 publications

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“…Abbes Amira et al [8] had proposed a parameterizable and scalable architecture for fast Hadamard transform (FHT) with time and area complexities of O(2(W+1)) and O(2N2) respectively. Porto et al [9] presented a design space exploration on the forward 4x4 Hadamard Transform in H.264/AVC video coding standard. These implementations were described by VHDL and synthesized on the Altera Stratix device.…”

Section: Literature Surveymentioning

confidence: 99%

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

Agrawal¹,

Bairathi²,

Joshi³

2015

IJCA

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Transformation is one of the fundamental blocks of many signal processing applications. The Hadamard transform is useful in variety of application including data encryption methods and latest data compression algorithms such as JPEG extended range (JPEG XR), High Efficiency Video Coding (HEVC) etc. Hadamard transform is multiplier less technique and requires additions and subtractions only. In this paper, we have proposed an efficient method of 4 and 8 points Hadamard transformation using a parallel processing to achieve higher speed. The 8-point DHT has been realized with 4 points DHT implementation. The modules are synthesized using Xilinx ISE 14.2 software with the usage of inbuilt memory core generator for storing co-efficient values. The performance has been verified with area and timing analysis. The proposed implementation shows excellent results and also compared to previous works.

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Section: Literature Surveymentioning

confidence: 99%

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

Agrawal¹,

Bairathi²,

Joshi³

2015

IJCA

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“…To solve the second problem of finding better partition shape, we estimate spatial frequency components using Hadamard transform. 24 By making use of both variance and spatial frequency information, we obtain more optimal macro-block partitioning to reduce complexity of SAD calculations.…”

Section: Gupte and Bharadwajmentioning

confidence: 99%

Adaptive Global Elimination Algorithm for Low Power Motion Estimation<BR> (Journal of Low Power Electronics, Vol. 5, pp. 1–16 (2009))

Gupte¹,

Bharadwaj²

2009

Journal of Low Power Electronics

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Motion estimation typically consumes 50% to 70% of total power in video encode application. Optimizing the power consumption of motion estimation process is of great importance to low power video applications. Power dissipation increases with computational complexity. Reduction in motion estimation complexity is usually associated with increase in bit rate and a loss of quality. We explore a set of algorithms that reduce the complexity of motion estimation by adaptively changing the matching complexity based on macro-block features yet have only a modest cost in terms of bit rate increase and quality loss. The adaptive techniques are applied to the global elimination algorithm, which is a well known motion estimation algorithm. The global elimination algorithm uses fixed partition sizes and shapes irrespective of the nature of the macro-block. We show that by adapting the partition sizes and shapes according to the macro-block features such as variance and Hadamard coefficients, the computational complexity of global elimination algorithm can be significantly reduced with only a small increase in bit rate. We also propose a novel center-biased search order that uses early termination method designed to work with the global elimination algorithm. The adaptive match and center-biased search together result in around 57% reduction in computational complexity and 50% reduction in power dissipation compared to the original global elimination algorithm.

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“…In [16], the authors explore the Hadamard separability property, using two RAMs to store intermediary transform results. The lines and columns are transposed by a so-called "ping-pong" buffer, emulating a transpose buffer as defined in [17].…”

Section: Introductionmentioning

confidence: 99%

“…The lines and columns are transposed by a so-called "ping-pong" buffer, emulating a transpose buffer as defined in [17]. Also in [16], the pipeline depth and its positioning are explored to build fully parallel Hadamard transform architectures. Unlike these, some works on SATD do not apply the separability property of the Hadamard Transform.…”

Section: Introductionmentioning

confidence: 99%

Exploring Optimized Hadamard Methods to Design Energy-Efficient SATD Architectures

Cancellier¹,

Seidel²,

Bräscher³

et al. 2020

JICS

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State-of-the-art video coding tools are submitted to severe performance and energy consumption requirements resulting from high complexity of video standards and from limited energy budgets of portable mobile devices. While providing most of the compression gains, inter frame and intra frame prediction techniques are the most demanding steps, since they compare a huge number of blocks. In such a process, the similarity metric employed affects both the quality of compression and the calculation effort. In this paper we propose the use of Hadamardbased Sum of Absolute Transformed Differences (SATD), in replacement of the traditionally used Sum of Absolute Differences (SAD), as a means of improving the efficiency of video coding. To allow that we explore two Hadamard Transform methods to design efficient SATD architectures, one using the Fast Hadamard Transform (FHT) butterfly and another one using the so-called Transform-Exempted (TE) SATD algorithm. Those methods were combined with architectural decisions (full parallelism, full parallelism with pipelining or multi-cycling) to build a total of six Hadamard-based SATD architectures that were synthesized for a commercial 45nm standard cell library for two operating frequencies. The architectures were simulated with pixel block data to obtain realistic dynamic power and energy estimates. The TE-SATD architectures achieved the lowest energy results: down to 13.13 pJ/SATD in the case of parallel architecture with pipeline. However, considering also the area results when evaluating energy, the best results are given by both methods using multi-cycling (transpose buffer): nearly 20.75 pJ/SATD with up to 63.54% smaller area compared with fully parallel architectures.

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Design space exploration on the H.264 4/spl times/4 Hadamard transform

Cited by 8 publications

References 5 publications

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

Adaptive Global Elimination Algorithm for Low Power Motion Estimation<BR> (Journal of Low Power Electronics, Vol. 5, pp. 1–16 (2009))

Exploring Optimized Hadamard Methods to Design Energy-Efficient SATD Architectures

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