Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization

Abstract

Modern SoC systems consist of general-purpose processor cores augmented with large numbers of specialized accelerators. Building such systems requires a design flow allowing the design space to be explored at the system level with an appropriate strategy. In this paper, we describe a methodology allowing to explore the design space of power-performance heterogeneous SoCs by combining an architecture simulator (gem5-Aladdin) and a hyperparameter optimization method (Hyperopt). This methodology allows different types of parallelism with loop unrolling strategies and memory coherency interfaces to be swept. The flow has been applied to a convolutional neural network algorithm. We show that the most energy efficient architecture achieves a 2x to 4x improvement in energy-delay-product compared to an architecture without parallelism. Furthermore, the obtained solution is more efficient than commonly implemented architectures (Systolic, 2D-mapping, and Tiling). We also applied the methodology to find the optimal architecture including its coherency interface for a complex SoC made up of six accelerated-workloads. We show that a hybrid interface appears to be the most efficient; it reaches 22% and 12% improvement in energy-delay-product compared to just only using non-coherent and only LLC-coherent models, respectively.

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs

“…Chen et al [16] ✓ Cota et al [23] ✓ ✓ Fusion [45] ✓ ✓ gem5-aladdin [6,22,72] ✓ ✓ ✓ Spandex [1] ✓ ESP [35,36] ✓ ✓ ✓ NVDLA [60] ✓ Buffets [63] ✓ Kurth et al [46] ✓ Cavalcante et al [13] ✓ BiC [29] ✓ Cohesion [44] ✓ ARM ACE/ACE-Lite [3] ✓ ✓ ✓ Xilinx Zynq [56,59,68] ✓ ✓ Power7+ [8] ✓ Wirespeed [30] ✓ Arteris Ncore [11] ✓ ✓ CAPI [79] ✓ OpenCAPI [61] ✓ CCIX [14,15] ✓ ✓ Gen-Z [32] ✓ CXL [24] ✓ ✓…”