Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs

Zuckerman, Joseph D.; Giri, Davide; Kwon, Jihye; Mantovani, Paolo; Carloni, Luca P.

doi:10.1145/3466752.3480065

Cited by 13 publications

(4 citation statements)

References 74 publications

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“…They have access to the physical memory of the system through a level of the memory hierarchy. Without loss of generality, we assume that they are connected to the LLC, which is located on the chip and shared between cores and acceleratorswhich is a common choice adopted by SoC designers [7], [8], [19], [22], [23]. They are equipped with a DMA controller to load/store data from/to the LLC without CPU intervention.…”

Section: A Architectural Referencementioning

confidence: 99%

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IXIAM: ISA EXtension for Integrated Accelerator Management

et al. 2023

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During the last years, hardware accelerators have been gaining popularity thanks to their ability to achieve higher performance and efficiency than classic general-purpose solutions. They are fundamentally shaping the current generations of Systems-on-Chip (SoCs), which are becoming increasingly heterogeneous. However, despite their diffusion, a standard, general solution to manage them while providing speed and consistency has not yet been found. Common methodologies rely on OS mediation and a mix of user-space and kernel-space drivers, which can be inefficient, especially for fine-grained tasks. This paper addresses these sources of inefficiencies by proposing an ISA eXtension for Integrated Accelerator Management (IXIAM), a cost-effective HW-SW framework to control a wide variety of accelerators in a standard way, and directly from the cores. The proposed instructions include reservation, work offloading, data transfer, and synchronization. They can be wrapped in a high-level software API or even integrated into a compiler. IXIAM features also a user-space interrupt mechanism to signal events directly to the user process. We implement it as a RISC-V extension in the gem5 simulator and demonstrate detailed support for complex accelerators, as well as the ability to specify sequences of memory transfers and computations directly from the ISA and with significantly lower overhead than driver-based schemes. IXIAM provides a performance advantage that is more evident for small and medium workloads, reaching around 90¢ in the best case. This way, we enlarge the set of workloads that would benefit from hardware acceleration.

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Section: A Architectural Referencementioning

confidence: 99%

“…According (c) The module forwards the UIM to the mth core, which delegated to the accelerator the command that generated this user-space interrupt. to state-of-the-art, accelerator coherence (or lack of) in SoCs can be addressed in four different ways [23], [29]:…”

Section: A Memory Coherencymentioning

confidence: 99%

IXIAM: ISA EXtension for Integrated Accelerator Management

et al. 2023

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“…After it is started, the accelerator issues DMA requests, which are sent to the ESP memory hierarchy using one of four cache-coherence modes. The different cachecoherence modes operate completely transparently to the accelerator and can be selected at runtime based on the needs of the accelerator and the overall status of the system [23,40]. When the accelerator completes, it sends an interrupt that resumes the execution of the software thread that invoked it.…”

Section: The Esp Architecturementioning

confidence: 99%

Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP

Zuckerman¹,

Mantovani²,

Giri³

et al. 2022

Preprint

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Heterogeneous, multicore SoC architectures are a critical component of today's computing landscape. However, supporting both increasing heterogeneity and multicore execution are significant design challenges. Meanwhile, the growing RISC-V and open-source hardware (OSH) movements have resulted in an increased number of open-source RISC-V processor implementations; however, there are fewer open-source SoC design platforms that integrate these processor cores. We present modifications to ESP, an open-source SoC design platform, to enable multicore execution with the RISC-V CVA6 processor. Our implementation is modular and based on standardized interfaces. These properties simplify the integration of new cores. Our modifications enable RISC-V-based SoCs designed with ESP for FPGA to boot Linux SMP and execute multithreaded applications. Coupled with ESP's emphasis on accelerator-centric architectures, our contributions enable the seamless design of a wide range of heterogeneous, multicore SoCs. CCS CONCEPTS• Computer systems organization → Multicore architectures; System on a chip; Heterogeneous (hybrid) systems.

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“…Heterogeneous architectures are established in mobile and high-performance applications: silicon-proven industrial [6]- [8] and academic [9], [10] systems-on-chip (SoCs) typically target large power envelopes or multiple AC cores. However, heterogeneity is now penetrating the internet of things (IoT) extreme-edge and TinyML domains where power and cost constraints are extremely tight.…”

Section: Introduction With Koomey's Lawmentioning

confidence: 99%

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Ottaviano

Benz

Scheffler

et al. 2023

IEEE Trans. Circuits Syst. II

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Power and cost constraints in the internet-ofthings (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous architectures. These designs use energyefficient application-class host processors to coordinate computespecialized multicore accelerators, amortizing the architectural costs of operating system support and external communication. This brief presents Cheshire, a lightweight and modular 64-bit Linux-capable host platform designed for the seamless plug-in of domain-specific accelerators. It features a unique low-pin-count DRAM interface, a last-level cache configurable as scratchpad memory, and a DMA engine enabling efficient data movement to or from accelerators or DRAM. It also provides numerous optional IO peripherals including UART, SPI, I2C, VGA, and GPIOs. Cheshire's synthesizable RTL description, comprising all of its peripherals and its fully digital DRAM interface, is available free and open-source. We implemented and fabricated Cheshire as a silicon demonstrator called Neo in TSMC's 65nm CMOS technology. At 1.2 V, Neo achieves clock frequencies of up to 325 MHz while not exceeding 300 mW in total power on dataintensive computational workloads. Its RPC DRAM interface consumes only 250 pJ/B and incurs only 3.5 kGE in area for its PHY while attaining a peak transfer rate of 750 MB/s at 200 MHz.

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Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs

Cited by 13 publications

References 74 publications

IXIAM: ISA EXtension for Integrated Accelerator Management

IXIAM: ISA EXtension for Integrated Accelerator Management

Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

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