Design space exploration of caches using compressed traces

Li, Xianfeng; Negi, Hemendra Singh; Mitra, Tulika; Roychoudhury, Abhik

doi:10.1145/1006209.1006227

Cited by 19 publications

(11 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The time complexity of their algorithm for searching procedure is O((log 2 (N) + 1) × A) and the time complexity for maintaining the binomial tree is O((log 2 (N) + 1) × A), where N is the size of the cache and A is the associativity of the cache. Li in [11] then extends the work in [10] by introducing a method to compress the program trace for reducing the cache simulation time.…”

Section: Related Workmentioning

confidence: 98%

Finding optimal L1 cache configuration for embedded systems

Janapsatya

Ignjatović

Parameswaran

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

View full text Add to dashboard Cite

Modern embedded system execute a single application or a class of applications repeatedly. A new emerging methodology of designing embedded system utilizes configurable processors where the cache size, associativity, and line size can be chosen by the designer. In this paper, a method is given to rapidly find the L1 cache miss rate of an application. An energy model and an execution time model are developed to find the best cache configuration for the given embedded application. Using benchmarks from Mediabench, we find that our method is on average 45 times faster to explore the design space, compared to Dinero IV while still having 100% accuracy.

show abstract

Section: Related Workmentioning

confidence: 98%

Finding optimal L1 cache configuration for embedded systems

Janapsatya

Ignjatović

Parameswaran

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

View full text Add to dashboard Cite

show abstract

“…However, address traces could be very big even for a small program and they have to be compressed for practical usage. Simulation methodology that operates directly on a compressed trace have been presented in [Li et al 2004]. Recently, Mohammad et al proposed a single pass simulation framework [Haque et al 2009].…”

Section: Trace Driven Simulationmentioning

confidence: 99%

An analytical approach for fast and accurate design space exploration of instruction caches

Liang

Mitra

2013

ACM Trans. Embed. Comput. Syst.

Self Cite

View full text Add to dashboard Cite

Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip area. Simulation, in particular trace-driven simulation, is widely used to estimate cache hit rates. However, simulation is too slow to be deployed in design space exploration, especially when there are hundreds of design points and the traces are huge. In this paper, we propose a novel analytical approach for design space exploration of instruction caches. Given the program control flow graph (CFG) annotated only with basic block and control flow edge execution counts, we first model the cache states at each point of the CFG in a probabilistic manner. Then, we exploit the structural similarities among related cache configurations to estimate the cache hit rates for multiple cache configurations in one pass. Experimental results indicate that our analysis is 28 -2,500 times faster compared to the fastest known cache simulator while maintaining high accuracy (0.2% average error) in estimating cache hit rates for a large set of popular benchmarks. Moreover, compared to a state-of-the-art cache design space exploration technique, our approach achieves 304 -8086 times speedup and saves up to 62% energy and on average 7% for the evaluated benchmarks.

show abstract

“…Four of the popular speedup mechanisms applied to trace driven simulations are: 1) Compressed trace simulation, 2) Parallel simulation, 3) Sample-based simulation and 4) Single-pass simulation. Compressed trace simulation [20,22,26,27] prunes redundant information to compress the application's memory access trace, resulting in a reduced simulation time. Parallel simulation techniques perform the simulation of a group of cache configurations in parallel on multiple processors [4,10,13].…”

Section: Related Workmentioning

confidence: 99%

DIMSim

Haque

Ragel

Ambrose

et al. 2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

View full text Add to dashboard Cite

It is of critical importance to satisfy deadline requirements for an embedded application to avoid undesired outcomes. Multiprocessor System-on-Chips (MPSoCs) play a vital role in contemporary embedded devices to satisfy timing deadlines. Such MPSoCs include two-level cache hierarchies which have to be dimensioned carefully to support timing deadlines of the application(s) while consuming minimum area and therefore minimum power. Given the deadline of an application, it is possible to systematically derive the maximum time that could be spent on memory accesses which can then be used to dimension the suitable cache sizes. As the dimensioning has to be done rapidly to satisfy the time to market requirement, we choose a well acclaimed rapid cache simulation strategy, the single-pass trace driven simulation, for estimating the cache dimensions. Therefore, for the first time, we address the two main challenges, coherency and scalability, in adapting a single-pass simulator to a MPSoC with two-level cache hierarchy. The challenges are addressed through a modular bottom-up simulation technique where L1 and L2 simulations are handled in independent communicating modules. In this paper, we present how the dimensioning is performed for a two-level inclusive data cache hierarchy in an MPSoC. With the rapid simulation proposed, the estimations are suggested within an hour (worst case on considered application benchmarks). We experimented our approach with task based MPSoC implementations of JPEG and H264 benchmarks and achieved timing deviations of 16.1% and 7.2% respectively on average against the requested data access times. The deviation numbers are always positive meaning our simulator guarantees to satisfy the requested data access time. In addition, we generated a set of synthetic memory traces and used them to extensively analyse our simulator. For the synthetic traces, our simulator provides cache sizes to always guarantee the requested data access time, deviating below 14.5% on average.

show abstract

Design space exploration of caches using compressed traces

Cited by 19 publications

References 30 publications

Finding optimal L1 cache configuration for embedded systems

Finding optimal L1 cache configuration for embedded systems

An analytical approach for fast and accurate design space exploration of instruction caches

DIMSim

Contact Info

Product

Resources

About