Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective

Li, Jing; Ndai, Patrick; Goel, Ashish; Salahuddin, Sayeef; Roy, Kaushik

doi:10.1109/tvlsi.2009.2027907

Cited by 117 publications

(69 citation statements)

References 8 publications

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“…Magnetization in one of the layers (referred to as the pinned layer) is fixed in one direction. The other ferromagnetic layer (referred to as the free layer) is used for information storage [58] (see Figure 19b). Data writing is performed by using the spin-polarized current to change the magnetic orientation of the free layer with respect to the fixed layer in the MTJ device.…”

Section: Spin Transfer Torque Memorymentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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Section: Spin Transfer Torque Memorymentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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“…The common approach to calculating STT-MRAM failure probabilities assumes distributions for R MTJ and the TMR of the MTJ [21], which may be physically incorrect. We now show how STT-MRAM failure probabilities may be calculated without the need to assume distributions for R MTJ and TMR of the MTJ.…”

Section: Modeling Stt-mram Failuresmentioning

confidence: 99%

“…When multifinger transistors are used in the bit-cell design, the effective access transistor width may be varied using two word-lines instead of one (Fig. 3.11), and is called the 2T-1MTJ design [21]. Word line 1 is used during read operations to switch M1 ON and OFF, while word line 2 keeps M2 OFF.…”

Section: The 2t-1mtj Stt-mram Bit-cellmentioning

confidence: 99%

Design and Optimization of Spin-Transfer Torque MRAMs

Fong

Choday

Roy

2015

More Than Moore Technologies for Next Generation Computer Design

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In this chapter, reviews the basics and modeling of spin-transfer torque magnetic RAM (STT-MRAM) for circuit-level failure analysis. A methodology for analyzing failures in STT-MRAM bit-cells is also presented. The optimization of STT-MRAM bit-cells using the presented framework is then discussed, along with several circuit and array architecture-level failure mitigation techniques. We will show that despite the relatively high write energy in STT-MRAM, large capacity last level caches based on STT-MRAM can be more energy efficient than their SRAM counterparts due to the unique characteristics of STT-MRAM.The cache capacity of high-performance microprocessors is increasing as transistor technology is scaled down. Since the leakage power also increases exponentially with the scaling down of transistor technology, the power dissipation of on-chip caches is an increasingly dominant component of power dissipation in highperformance microprocessors. Non-volatile memories have been proposed as a solution for mitigating the increasing power dissipation in high-performance onchip caches. Among the currently available non-volatile memory technologies, only spin-transfer torque magnetic random access memory (STT-MRAM) has the desired characteristics for high-performance on-chip cache applications [1]. In this chapter, we discuss the design optimization and modeling of STT-MRAMs, and its potential application in high-performance on-chip caches.

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“…To improve the hardness of STT-MRAM to the soft and hard errors, some design strategies and considerations [20][21][22][23][24] for reliability enhancement of STT-MRAM have been presented recently. For instance, to reduce the error rate for the suppressed read current, concept of '1'/'0' dual-array equalized reference is able to generate a precise reference for stable read operation [21].…”

Section: Potential Solutionsmentioning

confidence: 99%