Design-oriented estimation of thermal noise in switched-capacitor circuits

Abstract

Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter.

Multi-stage sigma-delta ADC with noise-coupling technology

“…In addition, thermal noise as an important noise exists within the circuit and mainly includes MOS-transistor noise and kT/C noise [8]. In practice, modulators are usually realized by using the switched-capacitor (SC) structure, and the switch can be regarded as a resister with on-resistance [9]. Hence, in general, attention is focused on the kT/C noise in the SC circuit.…”

A simple time domain approach to noise analysis of switched capacitor circuits

“…Due to this fact, the PSD of the sampled output noise will be heavily aliased and therefore the spectrum of the sampled noise signal v out (n) is nearly white [4] where v out (n) is the value of the sampled noise at the end of the previous tracking interval (nT ). The aliasing increases the PSD of the noise but the MS value of the sampled signal v out (n) in Fig.…”

“…2c receptively where v in = 0 is assumed for simplicity. The MS value of sampled noise on C 1 during ϕ 1 = "1" due to witches M 1 and M 3 is (kθ/C 1 ) as explained in [4]. This sampled noise voltage v nC1,1 (n) is delivered to C 2 in the next phase during ϕ 2 = "1".…”

“…Another method presented in [2] is based on an approximate analytical analysis of the circuit. Later; more elaborated analytical analysis are presented in [3,4] based on this method.…”

Noise analysis and optimization of a unity gain sampler

“…To eliminate those unwanted charge injection, a type of SC UG sampler with elaborate designed switch timing is introduced [1] [2]. Although it has better static performance, the temporal noise is inevitably increased by the extra two switches and timing operation [3] [4].…”