Design Optimization of a Transimpedance Amplifier for a Fiber Optic Receiver

Abstract

This paper presents the design of a framework for the optimization of a low-power, low-noise, broadband transimpedance amplifier to be used in a fiber optic transceiver. The design is implemented using a 180 nm six-metal-layer digital CMOS process with a 1.8V supply. The performances achieved are a gain of 78.34 dB , a bandwidth of 2.21 GHz, an input referred current noise of 11.91 pA/Hz 1/2 , and a power dissipation of 13.5 mW.

Polarization division multiplexing for optical data communications

“…In this research work for the receiver chip channel design we use slower circuit design that has amplifier and comparator with hysteresis that operate in the MHz frequency range. For future VLC PDM high-speed system design in the multiple GHz range we will use transimpedance amplifier (TIA) designs which are well described in the literature [2,6,39,40,58,59,61].…”

A Multi-Stage TIA based on Cascoded-Inverter Structures for Low-power Applications

“…The output stage, which employs an active inductor, not only provides proper output swing, but also resonates with the capacitive load and provides extra frequency bandwidth. Also, in designing the proposed TIA, the G m /I D technique [21]- [24] is used to properly extract the ratio of width and length of each transistor in 90nm CMOS technology. This method provides a clear vision for the designer and hence a useful way to estimate dimensions of transistors [24].…”