Many architects believe that major improvements in cost-energyperformance must now come from domain-specific hardware. This paper evaluates a custom ASIC-called a Tensor Processing Unit (TPU)-deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile responsetime requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

Many architects believe that major improvements in cost-energyperformance must now come from domain-specific hardware. This paper evaluates a custom ASIC-called a Tensor Processing Unit (TPU)-deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile responsetime requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X-30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X-80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

The need for temporal-spatial control over the release of biologically active molecules has motivated efforts to engineer novel drug delivery-on-demand strategies actuated via light irradiation. Many systems, however, have been limited to in vitro proof-of-concept due to biocompatibility issues with the photo-responsive moieties or the light wavelength, intensity and duration. To overcome these limitations, this paper describes a light actuated drug delivery-on-demand strategy that uses visible and near infrared (NIR) light and biocompatible chromophores: cardiogreen, methylene blue and riboflavin. All 3 chromophores are capable of significant photothermal reaction upon exposure to NIR and visible light, and the amount of temperature change is dependent upon light intensity, wavelength as well as chromophore concentration. Pulsatile release of bovine serum albumin (BSA) from thermally-responsive hydrogels was achieved over 4 days. These findings have the potential to translate light actuated drug delivery-on-demand systems from the bench to clinical applications that require explicit control over the presentation of biologically active molecules.

Design of tunable multi-band time delay elements based on frequency translation is presented. The proposed topology exhibits time delay of multiple periods of the RF carrier. Two possible implementations of the proposed idea are presented and simulation results are shown for one such implementation. The implemented circuit exhibits an envelope delay of 2.5 ns with the RF carrier delay tunable from 0 • to 360 • in 45 • steps in the 2.4 GHz ISM band.

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