Design, optimization, and implementation of a universal FFT processor

Abstract

There exist Fast Fourier transform (FFT) algorithms, called dimensionless 1 FFTs, that work independent of dimension. These algorithms can be configured to compute different dimensional DFTs simply by relabeling the input data and by changing the values of the twiddle factors occurring in the butterfly operations. This observation allows us to design an FFT processor, which with minor reconfiguring, can compute one, two, and three dimensional DFTs. In this paper we design a family of FFT processors, parameterized by the number of points, the dimension, the number of processors, and the internal dataflow, and show how to map different dimensionless FFTs onto this hardware design. Different dimensionless FFTs have different dataflows and consequently lead to different performance characteristics. Using a performance model we search for the optimal algorithm for the family of processors we considered. The resulting algorithm and corresponding hardware design was implemented using FPGA.

Formal datapath representation and manipulation for implementing DSP transforms

“…Although we do not know of any other instances of the tensor formula language being extended to support a general class of hardware implementations in this manner, it has been used in the process of designing special purpose hardware (e.g., an FFT processor in [7] and FFT cores in our previous work [8]). The important distinctions are that neither approach extends the formula language to describe datapath structure and that neither compiles from the formula to hardware; the formula is used to describe the algorithm only.…”

Automatic generation of customized discrete fourier transform IPs

“…Most pertinent to this paper, L n n/2 is the "perfect-shuffle" permutation (e.g., L 2 Only a single twiddle multiplier is needed in each C block because one of the two twiddle factors is always 1. dataflow as a log 2 (n)-by-n/2 grid of C blocks, where the columns are separated by the L n n/2 stride permutations. The regularity and structure in the dataflow is directly reflected by the product and tensor product in the Pease FFT formula (1) and is conducive to the concurrency parameterization employed by our core generator.…”

An assessment of high-level partitioning techniques for implementing discrete signal transforms on distributed hardware architectures

“…X [7] X [6] X [9] X [8] X [11] X [10] X [9] X [8] X [11] X [10] X Given that communication channels will probably represent the most constrained resource for highly connected algorithms such as the fast versions of DSTs, we use the cut size as a highlevel estimator that should translate to reduced latency on the implementation. The coarse node graph is partitioned with the objective of minimizing an objective function that considers the cost for communicating through the various architectural channels:…”

“…The implementation of these fast versions requires a regular but congested communication scheme among the various computational elements, which can dominate performance depending on the target architecture and the utilized partitioning strategy [7]. Some approaches have recurred to exhaustive methods to search for optimal partitions of an FFT, resulting in partitioning schemes similar to data allocation schemes proposed by researchers in the general purpose distributed system area [8]. This variety of treatments underlines the need for automated methods to exploit DST characteristics to improve their partitioning to DHAs.…”