An assessment of high-level partitioning techniques for implementing discrete signal transforms on distributed hardware architectures

Abstract

Abstract-Partitioning is an essential step in the implementation of algorithms to distributed hardware architectures (DHAs) such as multi-FPGA boards. While numerous approaches working at the structural level have been reported, techniques targeted at higher levels are less common. Moreover, when dealing with discrete signal transforms (DSTs), formulation-level partitioners for DHAs have been largely neglected. In this paper, we introduce a first approach towards a functionally-aware methodology that could provide improved results for the high-level partitioning of DSTs to DHAs. Our methodology has been devised through the study of DST partitioning techniques for DHA-similar systems, as well as general DST formulation techniques. An assessment performed on discrete Fourier transforms has achieved as much as 35% in latency reduction when compared to other general, high-level partitioning schemes.

Field-Programmable Wiring Systems

“…In many respects, the challenges in developing multipanel programmable wiring systems are similar to those in multi-FPGA systems. In multi-FPGA systems (driven by large-scale hardware emulation applications [41], [42]), problems in partitioning large designs [43], performing pin assignment [44], and ''spread-net'' (nets cutting across two or more FPGAs) routing [45] have been studied. Just as there are non-unique solutions to the routing problem within a particular programmable wiring system, there are also non-unique solutions to the global partitioning of the wiring problem into subproblems.…”

Functionally-aware Partitioning of Discrete Signal Transforms for Distributed Hardware Architectures

“…We hypothesize that awareness of such characteristics during partitioning will result in a more focused exploration of the design space and improved solution quality. To this end, we designed a methodology that incorporates formulation-level transformations and other DST-derived strategies throughout the highlevel partition process [6]. In this paper, we describe our methodology, emphasizing how DST-specific considerations influence the implementation of our partition optimization heuristic.…”