Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction Methodology

Lakshmikanthan, Preetham; Sahni, Kanika; Nunez, A.

doi:10.1109/socc.2006.283854

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…Similar to the method in Ref. [12], a single high threshold PMOS transistor is inserted between the pull-up and pull-down networks, which are composed of low threshold transistors. Extra NMOS and PMOS transistors are added in parallel with the pull-up and pull-down networks to keep the voltage potential between the source node of the high threshold transistor and power supply (V DD , and the drain node of the high threshold transistor and ground, at equivalent levels to minimize leakage in sleep mode.…”

Section: Mtcmos Threshold Gatesmentioning

confidence: 99%

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

Bailey¹,

Zahrani²,

Fu³

et al. 2008

Journal of Low Power Electronics

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This paper presents an ultra-low power circuit design methodology which combines the Multi-Threshold CMOS (MTCMOS) technique with quasi delay-insensitive (QDI) asynchronous logic, in order to solve the three major problems of synchronous MTCMOS circuits: (1) Sleep signal generation, (2) storage element data loss during sleep mode, and (3) sleep transistor sizing. In contrast to most power reduction methods that result in area overhead, the QDI asynchronous MTCMOS circuits are usually smaller than their original versions. Moreover, QDI circuits utilize handshaking protocols instead of clocks for circuit control, resulting in flexible timing requirements, which yields increased circuit robustness and allows for extreme supply voltage scaling to subthreshold region for further power reduction, without requiring any circuit modifications. This QDI asynchronous MTC-MOS methodology is used to design a 4-stage pipelined 8-bit × 8-bit unsigned multiplier, which is then compared against the original QDI design (i.e., without incorporating MTCMOS) and its synchronous version. All designs use the IBM 8RF-DM 0.13 m process. Results show 150× and 1.8× leakage power and active energy reductions on average in the QDI asynchronous MTCMOS design compared to the original QDI version, respectively.

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Section: Mtcmos Threshold Gatesmentioning

confidence: 99%

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

Bailey¹,

Zahrani²,

Fu³

et al. 2008

Journal of Low Power Electronics

View full text Add to dashboard Cite

show abstract

“…One major drawback of this method is that partitioning the circuit into appropriate logic blocks and sleep transistor sizing is difficult for large circuits. An alternative fine-grained architecture, shown in Figure 5, incorporates the MTCMOS technique within every gate [14], using low-Vt transistors for the Pull-Up Network (PUN) and Pull-Down Network (PDN) and a high-Vt transistor to gate the leakage current between the two networks. Two additional low-Vt transistors are included in parallel with the PUN and PDN to maintain nearly equivalent voltage potential across these networks during sleep mode (i.e., X1 is approximately VDD and X2 is approximately GND).…”

Section: Introduction To Mtcmosmentioning

confidence: 99%

Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology

Zhou

Parameswaran

Parsan

et al. 2015

JLPEA

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This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic

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Low-Power NCL Design

Smith

2009

Designing Asynchronous Circuits Using NULL Convention Logic (NCL)

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Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction Methodology

Cited by 8 publications

References 4 publications

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology

Low-Power NCL Design

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