Design of two-phase sinusoidal power clock and clocked transmission gate adiabatic logic circuit

Wang, Pengjun; Jian, Yu

doi:10.1007/s11767-005-0170-2

Cited by 8 publications

(4 citation statements)

References 7 publications

(11 reference statements)

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“…Be that as it may, because of the additional MOSFET diodes in charging and releasing way somewhat bigger power dissemination than QSERL circuits happen. Because of these difficulties with detailed adiabatic rationale circuits [11][12][13][14][15][16][17][18][19] we propose altered semi static vitality recuperation rationale (MQSERL) circuit. MQSERL acquires every one of the upsides of as of late detailed QSERL circuits with extra enhancement in power sparing by decreasing the non-adiabatic misfortunes just as adiabatic misfortunes.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

Mayilsamy¹,

Srinivasan²,

Sharmila³

2019

IJRTE

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This work depends on another methodology for limiting vitality utilization in semi static vitality recuperation rationale of Modified Quasi Static Energy Recovery Logic (MQSERL) circuit which includes enhancement by expelling the non-adiabatic misfortunes totally. Vitality recouping hardware dependent on adiabatic standards is a promising system driving towards low power superior circuit plan. The productivity of such circuits might be expanded by lessening the adiabatic and non-adiabatic misfortunes drawn by them amid the charging and recuperation tasks. In this paper, execution of the proposed rationale style is broke down and contrasted and CMOS in their agent inverters, entryways, flip- flop and snake circuits. Every one of the circuit was reproduced by test system of TANNER TOOL in 0.18μm innovation. In our proposed inverter the vitality proficiency has been enhanced to practically 30% and 20% up to 20MHz and 20fF outside load capacitance in contrast with CMOS and MQSERL circuits individually. Our proposed circuit gives vitality proficient execution up to 100 MHz and in this way it has ended up being utilized in superior VLSI hardware.

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Section: Introductionmentioning

confidence: 99%

Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

Mayilsamy¹,

Srinivasan²,

Sharmila³

2019

IJRTE

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“…There are several remedies to reduce adiabatic losses. Some of them are by extending the charging time, constant current charging [14] for capacitance through a resistance in a given time. Another important mechanism for energy saving in adiabatic circuits is to recover the adiabatic losses which were stored in load capacitance during charging can be recovered again with a dissipation that depends inversely on charging time.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic

Aditya¹,

Chenna²,

Neha³

2014

IOSRJVSP

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“…First one is by extending the charging time . The second way is constant current charging [8] for capacitance through 2 VLSI Design a resistance in a given time. Third method is by lowering the charging path resistance, which was not the case in CMOS.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

2013

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Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 m UMC technology. In our proposed (IQSERL) inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

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Design of two-phase sinusoidal power clock and clocked transmission gate adiabatic logic circuit

Cited by 8 publications

References 7 publications

Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

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