Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic

Aditya, K.; Chenna, Sai Prabhakar Rao; Neha, Dandu

doi:10.9790/4200-04430108

Cited by 1 publication

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“…The electricity consumption was once once lots less for 12T whereas larger output is offered for 10T. Simulation was performed 90nm science with mentor snap shots device [6].…”

Section: Introductionmentioning

confidence: 99%

4-bit Carry Look Ahead Adder Using MGDI Technique

Afridi¹

2021

IJRASET

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Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion Input) is cautioned in this work. The delay, location and energy trade off performs a integral role in VLSI. We already comprehend that designs which are of CMOS fashion occupy extra area might also eat extra strength consumption. The switching conduct of the circuit reason the heating up of integrated circuits affects the working stipulations of the purposeful unit. The adders are the most important parts of countless applications such as microprocessors, microcontrollers and digital signal processors and additionally in actual time applications. Hence it is necessary to minimize the adder blocks to format a perfect processor. This work is proposed on a 16 bit carry seem to be in advance adder is designed through using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI raise Look Ahead adder occupies 68% much less region and the strength consumption and the propagation extend additionally considerably reduces when in contrast to the traditional carry Look Ahead adder why because the variety transistors extensively reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation consequences of the proposed format carried out in Xilinx. Keywords: Delay, power dissipation, voltage, transistor sizing.

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“…The electricity consumption was once once lots less for 12T whereas larger output is offered for 10T. Simulation was performed 90nm science with mentor snap shots device [6].…”

Section: Introductionmentioning

confidence: 99%

4-bit Carry Look Ahead Adder Using MGDI Technique

Afridi¹

2021

IJRASET

View full text Add to dashboard Cite

show abstract

Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic

Abstract: Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred

Cited by 1 publication

References 14 publications

4-bit Carry Look Ahead Adder Using MGDI Technique

4-bit Carry Look Ahead Adder Using MGDI Technique

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