2021 IEEE Applied Power Electronics Conference and Exposition (APEC) 2021
DOI: 10.1109/apec42165.2021.9487160
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Design of three-level flying-capacitor commutation cells with four paralleled 650 V/60 A GaN HEMTs

Abstract: This paper presents two improved solutions (Vertical and Horizontal commutation cells) for three-level flying capacitor (FC) topologies with four 650 V/ 60 A (25 mΩ) GS66516T GaN (Gallium Nitride) HEMTs (High Electron Mobility Transistors) in parallel per switch intended to be used in a 540 V / 70 kVA power drive system. Both solutions were built and experimentally tested, as a buck converter, regarding switching speed (15.14 kV / µs max) and overvoltage (6 % max) for different current levels (7 A to 53 A).

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Cited by 4 publications
(2 citation statements)
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“…The best practice against stray inductance is to place the capacitor on the same side as transistors and use adjacent copper layers to reduce loop area [14]. Another approach for Flying Capacitor topologies is to intertwine capacitors from both sides of the switching cell [15].…”
Section: Development Of a Prototypementioning
confidence: 99%
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“…The best practice against stray inductance is to place the capacitor on the same side as transistors and use adjacent copper layers to reduce loop area [14]. Another approach for Flying Capacitor topologies is to intertwine capacitors from both sides of the switching cell [15].…”
Section: Development Of a Prototypementioning
confidence: 99%
“…PWM signals on bottom layer are shielded from power owing above by a source plane on the adjacent layer. A common practice to cage a signal is to place vias at regular interval, as in [15] where a similar shielding issue was encountered. However, since vias would reduce the tight power path on power planes and increase asymmetry between paired transistors, it was decided instead to surround bottom grid path with 2 source paths.…”
Section: B Paralleling Transistorsmentioning
confidence: 99%