In this work, we have systematically investigated the technique of low‐temperature AlN interlayer in MOCVD growth of double heterojunction high‐electron‐mobility transistors buffer stacks on 200 mm Si (111) substrates. We have demonstrated that a continuous compressive stress can be maintained by insertion of interlayers which compensated a large tensile stress during cooling for a thick buffer. This eventually led to a low wafer bow and a good surface quality that enabled wafers with full device stack meeting the specifications for processing in our 200 mm CMOS pilot line. We also demonstrated at both forward and reverse bias conditions a significantly improved vertical buffer breakdown voltage (which is defined at a leakage current of 1 µA/mm2 in the present work) of >500 V at 25 °C and >300 V at 150 °C, respectively. (© 2015 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)