Effects of buffer layers on the stress and morphology of GaN epilayer grown on Si substrate by MOCVD

Liu, Zhe; Wang, Xiaoliang; Wang, Junxi; Hu, Guoping; Guo, Lunchun; Li, Jianping; Li, Jinmin; Zeng, Yiping

doi:10.1016/j.jcrysgro.2006.10.028

Cited by 21 publications

(9 citation statements)

References 16 publications

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“…However, the smaller shift of the E 2 (high) phonon frequency of CPSS-GaN indicates that there is less residual strain. Therefore, superior surface morphology has been achieved, which agrees well with the results reported by Niu et al 17) and Liu et al 18) Consequently, the ameliorative channelbarrier interface enhances the carrier mobility in the InAlN/ GaN heterostructure grown on the CPSS. This heterostructure material will be processed into HEMTs and its performance will be reported later.…”

supporting

confidence: 89%

Improved carrier mobility of InAlN/GaN heterostructure grown on cone-shaped patterned sapphire substrate

Zhao

Zhang

Xue

et al. 2014

Jpn. J. Appl. Phys.

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InAlN/GaN heterostructures were grown on both patterned and planar sapphire substrates by metal–organic chemical vapor deposition. Hall measurements showed that both samples possessed similar two-dimensional electron gas densities, whereas the electron mobility of the heterostructure grown on a patterned substrate was evidently superior. The enhanced mobility was attributed to the reduced threading dislocation density and improved channel-barrier interface morphology. Furthermore, Raman measurement results showed that there was less residual compressive strain in the GaN grown on the pattered sapphire substrate, which could be the reason for the morphology improvement. Consequently, the patterned sapphire substrate is very promising for further improving the performance of high-electron-mobility transistors.

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supporting

confidence: 89%

Improved carrier mobility of InAlN/GaN heterostructure grown on cone-shaped patterned sapphire substrate

Zhao

Zhang

Xue

et al. 2014

Jpn. J. Appl. Phys.

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“…In some cases, an SL may even increase the number of dislocations. 7 There are a moderate number of adjustable parameters in SL construction, which may not be independent with respect to TD blocking. This leads to a large problem space over which to design and test SLs, while, at the same time, the rules for how each of these parameters might influence dislocation blocking are unclear.…”

Section: Introductionmentioning

confidence: 99%

Simulations of Dislocations in CdZnTe/SL/Si Substrates

Ciani

Chung

2009

Journal of Elec Materi

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Discrete dislocation dynamics simulations were employed to study the primary mechanisms by which superlattices (SLs) block threading dislocations (TDs) from reaching the surface of a composite CdZnTe/SL/Si substrate. We found that the difference in strain (composition) across layer boundaries played a key role as to whether a TD might veer away or continue across. We also found that, while the distance between interfaces had little effect on the motion of a single TD, it could have an impact on the dislocation tangle as a whole and should be considered carefully in SL design. We discuss our results in relation to the design of SLs for TD blocking. INTRODUCTIONLattice-matched substrates with large areas are required to obtain economy of scale for the production of high quality long wave infrared (LWIR) Hg 1Àx Cd x Te (MCT) based devices. The best candidate for this task is the composite CdTe/Si substrate; however, high threading dislocation (TD) densities (>10 6 cm À2 ) at the surfaces of CdTe/Si substrates prohibit their effective use for (LWIR) detectors. Johnson et al. 1 showed that R 0 A j (the resistance at zero-bias 9 the junction area) begins to plateau toward its highest value as the etch pit density (EPD) drops below 5 9 10 5 cm À2 . For operation at 78 K, 5 9 10 5 cm À2 is a good target EPD. 2 The achievement of this final device EPD would require the substrate to have an even lower EPD, as the number of TDs increases inside the final MCT layer, 3 even when grown on lattice-matched substrates. To date, the best annealing strategies for CdTe/Si routinely attain the 10 6 cm À2 level, and densities as low as 5 9 10 5 cm À2 have been achieved. 4 Superlattices (SLs) have been observed to block the rise of TDs, reducing the number reaching the free surface in both III-V 5-7 and II-VI 8-11 semiconductor materials, although their ability to do so varies. In some cases, an SL may even increase the number of dislocations. 7 There are a moderate number of adjustable parameters in SL construction, which may not be independent with respect to TD blocking. This leads to a large problem space over which to design and test SLs, while, at the same time, the rules for how each of these parameters might influence dislocation blocking are unclear.In this paper we present results of discrete dislocation dynamics (DDD) 12,13 simulations investigating strategies for dislocation blocking via variable SL periodicities. The number of equations that govern the dislocations, their mutual interactions, and interactions with surfaces and interfaces, is far too large to be tractable by hand. DDD provides a means by which the equations can be integrated numerically and enables SL design parameters to be investigated systematically. Although, by now, the general parameter space for SL layer growth and TD mechanisms are wellunderstood, qualitative rules that govern their intersection still remain largely uncertain. In this work we studied (1) how the individual layer thickness affects the ability of TDs to encounter the next layer, there...

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“…The interest in growing epitaxial layers of binary semiconductor compounds A 3 B 5 , A 2 B 6 , and A 4 B 6 on silicon substrates (for instance, GaAs/GeSi/Si [1], GaN/AlN/Si [2], and HgCdTe/Si [3]) has been recently increased. This is related to solving the problem of technological matching of optoelectronic devices on the basis of binary compounds with the silicon-based technology.…”

Section: Introductionmentioning

confidence: 99%

“…It is seen in Fig. 1a and b that such reactions are possible between dislocations with the Burger's vectors whose directions are denoted by the numbers (1) and (4), (2) and (3), (5) and (8), and (6) and (7), i.e. pairs of dislocations that lie in {111} planes inclined to different sides from the (11 0) axis.…”

Section: Introductionmentioning

confidence: 99%

Formation of edge misfit dislocations in GexSi1−x (x∼0.4–0.5) films grown on misoriented (001)→(111) Si substrates

Bolkhovityanov¹,

Deryabin²,

Гутаковский³

et al. 2008

Journal of Crystal Growth

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Effects of buffer layers on the stress and morphology of GaN epilayer grown on Si substrate by MOCVD

Cited by 21 publications

References 16 publications

Improved carrier mobility of InAlN/GaN heterostructure grown on cone-shaped patterned sapphire substrate

Improved carrier mobility of InAlN/GaN heterostructure grown on cone-shaped patterned sapphire substrate

Simulations of Dislocations in CdZnTe/SL/Si Substrates

Formation of edge misfit dislocations in GexSi1−x (x∼0.4–0.5) films grown on misoriented (001)→(111) Si substrates

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