Design of the IBM z15 microprocessor

Saporito, Anthony; Recktenwald, M.; Jacobi, Christian; Koch, G.; Berger, D. P. D.; Sonnelitter, Robert; Walters, C. R.; Lee, J.-S.; Lichtenau, Cedric; Mayer, U.; Herkel, E.; Payer, Stefan; Mueller, Silvia Melitta; Papazova, V. K.; Ambroladze, E. M.; Bronson, T.

doi:10.1147/jrd.2020.3008119

Cited by 6 publications

(4 citation statements)

References 3 publications

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“…Nevertheless, there are some common types of operations that happen across a wide range of applications. Such examples are data sorting [72], compression [2,109] or cryptography [18]. IBM Z has a long history of implementing hardware accelerators for such tasks in cooperation with the firmware and software teams to enable best possible end to end value from those accelerators.…”

Section: Introductionmentioning

confidence: 99%

“…IBM Telum is the next generation chip for IBM z16 and LinuxONE systems [37] addressing the needs of enterprise class workloads. It provides improved performance, and system capacity in comparison to the predecessor z15 [9,72,101]. Figure 1 shows a die photo of the Telum chip.…”

Section: Introductionmentioning

confidence: 99%

“…IBM z15 [9,72,101] and prior system generations [10,11,17,28,50,51,80,95,96] implemented shared physical L3 caches on the processor chip, and had a separate chip that implemented a large L4 cache. The Telum design implements all of that logic in a single chip, and opts to quadruple the L2 cache to 32 MB with very low latency.…”

Section: Introductionmentioning

confidence: 99%

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AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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IBM Telum is the next generation processor chip for IBM Z and LinuxONE systems. The Telum design is focused on enterprise class workloads and it achieves over 40% per socket performance growth compared to IBM z15. The IBM Telum is the first server-class chip with a dedicated on-chip AI accelerator that enables clients to gain real time insights from their data as it is getting processed.Seamlessly infusing AI in all enterprise workloads is highly desirable to get real business insight on every transaction as well as to improve IT operation, security, and data privacy. While it would undeniably provide significant additional value, its application in practice is often accompanied by hurdles from low throughput if run on-platform to security concerns and inconsistent latency if run off-platform. The IBM Telum chip introduces an on-chip AI accelerator that provides consistent low latency and high throughput (over 200 TFLOPS in 32 chip system) inference capacity usable by all threads. The accelerator is memory coherent and directly connected to the fabric like any other general-purpose core to support low latency inference while meeting the system's transaction rate. A scalable architecture providing transparent access to AI accelerator functions via a non-privileged general-purpose core * This paper is part of the Industry Track of ISCA 2022's program.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…When it comes to ways to implement higher radix dividers, prior works focus on enhancing the complexity and criticality of SRT-based radix dividers [37,38]. Moreover, a combination of two or more alternatives together could be another way.…”

Section: Introductionmentioning

confidence: 99%

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Xia

Liu

et al. 2021

Applied Sciences

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Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point division in actual microprocessors, this paper proposes a low-latency architecture with a multi-precision architecture for floating-point division which will meet the IEEE-754 standard. There are three parts in the floating-point division design: pre-configuration, mantissa division, and quotient normalization. In the part of mantissa division, based on the fast division algorithm, a Predict–Correct algorithm is employed which brings about more partial quotient bits per cycle without consuming too much circuit area. Detailed analysis is presented to support the guaranteed accuracy per cycle with no restriction to specific parameters. In the synthesis using TSMC, 90 nm standard cell library, the results show that the proposed architecture has ≈63.6% latency, ≈30.23% total time (latency × period), ≈31.8% total energy (power × latency × period), and ≈44.6% efficient average energy (power × latency × period/efficient length) overhead over the latest floating-point division structure. In terms of latency, the proposed division architecture is much faster than several classic processors.

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