Design of SHA-1 &amp; SHA-2 MIPS processor using FPGA

Omran, Safaa S.; Jumma, Laith F.

doi:10.1109/ntict.2017.7976113

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…The ECDSA use a much smaller keys to obtain the same level of security of RSA. The SHA-1, SHA-2 (SHA-224 and SHA-256) is very well-known algorithm and SHA-2, which takes fewer time to generate the key (Omran and Jumma, 2017). This algorithm key length is 512 bits and considering hexadecimal Y [0-15] words of 32 bits.…”

Section: Literature Riviewmentioning

confidence: 99%

Enhanced Blockchain Transaction: A Case of Food Supply Chain Management

Amin¹,

Zuhairi²,

Saadat³

2019

J. Eng. Appl. Sci.

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Distributed ledger technology is an immutable data storage and transparent system, which is a constituent component that empowers the Food supply Chain Management (FSCM). Due to the immutable data feature, the scalability of blockchain technology is quite a challenge. In essence, blockchain data may grow rapidly as compared to the existing approach, and such circumstances is an issue that need to be addressed. Also, high volumes of data process for each transaction verification couple with long period of time for computation, lead to high overhead and resource consumption. This study discusses improved methods to reduce the amount of data generated by system. The proposed method employs the header verification system for transaction to reduce data growth and data processing time. During transaction, this method will verify only the header file information with using Merkle tree. This system is able to store each transaction of a node and form blockchain. Subsequently, each node is capable to verify valid transactions only by use of header data without maintaining full data of blockchain. The expected outcome of the scheme is the significant decrease of data growth in blockchain.

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Section: Literature Riviewmentioning

confidence: 99%

Enhanced Blockchain Transaction: A Case of Food Supply Chain Management

Amin¹,

Zuhairi²,

Saadat³

2019

J. Eng. Appl. Sci.

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“…A detailed study has been carried out on the existing hardware designs of MISTY1, KASUMI, AES, SHA-1, CAMELLIA and SAFER [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The review covered the comparison of performance parameters i.e.…”

Section: Introductionmentioning

confidence: 99%

“…In comparison to high throughput encryption cores, compact designs make use of the logic optimization techniques for transformation functions and s-boxes using combinational logic [5][6][7][8][9][10], [12][13][14][15][16][17][18], [21], [22]. Besides, re-utilization methodologies have also been implemented exploiting the rolling-feature of the architecture.…”

Section: Introductionmentioning

confidence: 99%

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Yasir¹,

Wu²,

Chen³

et al. 2018

RADIOENGINEERING

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In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.

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Digital Data Identification for Deduplication Process using Cryptographic Hashing Techniques

Sujatha

Raj

2021

2021 International Conference on Intelligent Technologies (CONIT)

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Design of SHA-1 & SHA-2 MIPS processor using FPGA

Cited by 5 publications

References 4 publications

Enhanced Blockchain Transaction: A Case of Food Supply Chain Management

Enhanced Blockchain Transaction: A Case of Food Supply Chain Management

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Digital Data Identification for Deduplication Process using Cryptographic Hashing Techniques

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