Design of Safe Two-Wire Interface-Driven Chip-Scale Neurostimulator for Visual Prosthesis

Jung, Louis H.; Shany, Nitzan; Emperle, Alexander; Lehmann, Torsten; Byrnes-Preston, Phil; Lovell, Nigel H.; Suaning, Gregg J.

doi:10.1109/jssc.2013.2264136

Cited by 21 publications

(14 citation statements)

References 30 publications

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“…TWI consist of two wires Serial Clock Line (SCL) and Serial Data Line (SDA). [6] CIE by the SCL generates the clock signal and data to each device can be transmitted by the SDA. In this extension, SCL is used not only for the clock signal but it is also used for the analog detectors.…”

Section: Hybrid Extensionmentioning

confidence: 99%

Hybrid Extension for Advanced Technology Zone

Mach

2017

MATEC Web Conf.

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Abstract. This article deals with the software extension for metallic loops. This extension consists of using the binary signal which can be generated by the Control and Indicating Equipment (CIE) to unite analog and digital detectors. Designed improvement can be applied to all existing modes of analog CIE such as Normal Closed (NC), End of Line (EOL) or Advanced Technology Zone (ATZ). It can be also applied to all common digital bus.

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Section: Hybrid Extensionmentioning

confidence: 99%

Hybrid Extension for Advanced Technology Zone

Mach

2017

MATEC Web Conf.

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“…For high number of channels, monopolar stimulation is usually chosen to reduce the number of the electrodes for stimulation [18,19,[23][24][25]. However, a negative power supply -Vss is needed in such topology.…”

Section: Current Drivermentioning

confidence: 99%

“…The required HV of 24 V is generated by a 4-stage charge pump circuit, and a stimulus current of 40 μA is achieved. In [19], a neural stimulator for visual prosthesis was designed in 0.35 μm HV CMOS process, which can withstand supply voltage of 20 V. HV devices with drain-to-source breakdown voltages of 20 V were utilized in the output stage, allowing relative large voltage compliance across the stimulating electrodes. In L. Bisoni (2015) [20], an integrated neural stimulator for prosthetic applications in 0.35 μm HV CMOS process was presented, which could deliver a 400 Hz pulse train with 152 μs cathodic and anodic duration to a 33 kΩ resistor.…”

Section: Introductionmentioning

confidence: 99%

A high‐voltage stimulation chip for wearable stroke rehabilitation systems

Zeng

Shi

et al. 2015

Circuit Theory & Apps

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SUMMARYIn this work, an 8-channel high-voltage (HV) stimulation chip for the rehabilitation of stroke patients through surface stimulation is presented. The chip receives control data through its serial peripheral interface and can be controlled by an external microcontroller. It can accordingly generate biphasic stimulation currents with different amplitudes, duration time, frequencies, and polarities for each channel independently. The chip was designed and fabricated using X-FAB 0.35 μm HV mixed-signal process. Circuits were carefully designed to ensure their operations under HVs. Our measurement results showed that a supply voltage of as high as 75 V can be achieved, and the current driver can generate biphasic stimuli with current amplitudes up to 4 mA.

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“…Implantable microelectronic devices (IMDs) form another key category of devices that is significantly benefiting from advancements in WPT. Because eliminating the transcutaneous interconnects and large batteries that would otherwise be needed to operate IMDs over extended periods is necessary to reduce their invasiveness and improve patient safety [10]–[16]. …”

Section: Introductionmentioning

confidence: 99%

A Multicycle Q-Modulation for Dynamic Optimization of Inductive Links

Lee

Yeon

Ghovanloo

2016

IEEE Trans. Ind. Electron.

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This paper presents a new method, called multi-cycle Q-modulation, which can be used in wireless power transmission (WPT) to modulate the quality factor (Q) of the receiver (Rx) coil and dynamically optimize the load impedance to maximize the power transfer efficiency (PTE) in two-coil links. A key advantage of the proposed method is that it can be easily implemented using off-the-shelf components without requiring fast switching at or above the carrier frequency, which is more suitable for integrated circuit design. Moreover, the proposed technique does not need any sophisticated synchronization between the power carrier and Q-modulation switching pulses. The multi-cycle Q-modulation is analyzed theoretically by a lumped circuit model, and verified in simulation and measurement using an off-the-shelf prototype. Automatic resonance tuning (ART) in the Rx, combined with multi-cycle Q-modulation helped maximizing PTE of the inductive link dynamically in the presence of environmental and loading variations, which can otherwise significantly degrade the PTE in multi-coil settings. In the prototype conventional 2-coil link, the proposed method increased the power amplifier (PA) plus inductive link efficiency from 4.8% to 16.5% at (RL = 1 kΩ, d23 = 3 cm), and from 23% to 28.2% at (RL = 100 Ω, d23 = 3 cm) after 11% change in the resonance capacitance, while delivering 168.1 mW to the load (PDL).

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Design of Safe Two-Wire Interface-Driven Chip-Scale Neurostimulator for Visual Prosthesis

Cited by 21 publications

References 30 publications

Hybrid Extension for Advanced Technology Zone

Hybrid Extension for Advanced Technology Zone

A high‐voltage stimulation chip for wearable stroke rehabilitation systems

A Multicycle Q-Modulation for Dynamic Optimization of Inductive Links

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