Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology

Riyaz, Sadat; Sharma, Vijay Kumar

doi:10.1108/cw-08-2020-0199

Cited by 16 publications

(5 citation statements)

References 17 publications

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“…The clocking mechanism is used to determine data direction and pipeline. Four‐phase clock signals are employed to transfer data across the logic circuits of the mechanism 13,14 . The switch, hold, release, and relax phases make up the clocking mechanism, as shown in Figure 2.…”

Section: The History Of the Quantum‐dot Camentioning

confidence: 99%

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Zhou

2023

Int J Numerical Modelling

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In quantum electronics, quantum-dot cellular automata (CA) is a technology to replace current transistor-based technologies. It provides low-power, incredibly dense, and high-speed constructions at a nano-scale. Quantum-dot CA is a revolutionary nano-scale technology that overcomes various restrictions in metal-oxide technology and simplifies the construction of digital integrated circuits. On the other hand, the demultiplexer is a valuable component for optimizing the entire process in logical design. So, proper cell placement and associated clock zone become the most important design requirement for effective logic operation in demultiplexer. Also, redundancy in fault-tolerant circuits can increase the dependability of digital circuits. However, in this area, the studies are not adequate, and most of them suffer from improper use of clocking systems and inefficient circuit features such as fault-tolerant. As a result, the current study demonstrates a unique quantum-dot CA-based faulttolerant 1:2 demultiplexer design. The proposed method is verified by implementing the fault-tolerant gates and cell redundancy. Also, we look at the layouts' cells, area, latency, single-cell missing, single-cell displacement, and additional single-cell. We also use the famous simulator, QCADesigner, to model the proposed design. The proposed fault-tolerant 1:2 demultiplexer's effectiveness is also discussed. Sixty-eight cells and 0.04 μm 2 of occupied space make up the unique fault-tolerant 1:2 demultiplexer. The results showed that the proposed design is completely faults-tolerance regarding tolerant missing, displaced, and additional single cells faults.

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Section: The History Of the Quantum‐dot Camentioning

confidence: 99%

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Zhou

2023

Int J Numerical Modelling

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“…The fundamental unit for QCA nanotechnology is the QCA cell. A QCA cell consists of four quantum-dots [3]. Cell-to-cell interaction permits the data flow in QCA nanotechnology.…”

Section: Introductionmentioning

confidence: 99%

Parity Generators for Nanocommunication Systems Using QCA Nanotechnology

Sharma

2023

Period. Polytech. Elec. Eng. Comp. Sci.

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Quantum-dot cellular automata (QCA) nanotechnology has the capability to design highly-dense, ultra-low power, and high-speed digital circuits at ultra-deep sub-micron (ultra-DSM) level. QCA nanostructure provides a transistor-free operation that saves large energy dissipation as compared to the conventional metal oxide semiconductor field effect transistor (MOSFET) technology. In this paper, 3-input exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are presented using QCA cells. XOR and XNOR (XOR-XNOR) gates are further utilized to design the 2-, 3-, 4-, and 5-bit even and odd parity generators. The QCA-based 3-input XNOR gate is constructed using only 10 QCA cells and two clock phases. The target of the presented designs is to use the minimum count of QCA cells in a simplistic way to form the higher bit-size parity generators. The comparative analyses for the different performance metrics are showing that the developed designs are performing well for the cell count, latency, area, and layout cost as compared to the existing designs. Energy dissipation for the designs is calculated to check the energy efficiency by using the QCA Designer-E and QCA Pro tools.

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“…Equation (1) shows that OR and AND logic can be created by fixing one input at Logic 1 and Logic 0, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…Working‐technology nodes are continuously being scaled down to obtain small‐size electronic gadgets. Area‐efficient circuit design is a challenging task in the commonly used complementary metal–oxide–semiconductor (CMOS) technology because of the limitation of materials [1]. Therefore, exploration of different technologies is needed in the VLSI domain to enhance this field, especially in the ultra‐nanoscale region.…”

Section: Introductionmentioning

confidence: 99%

Single‐bit digital comparator circuit design using quantum‐dot cellular automata nanotechnology

Sharma

2022

ETRI Journal

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The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra‐nanoscale region. Circuit designers explore a new technology for the ultra‐nanoscale region, which is the quantum‐dot cellular automata (QCA). Low‐energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low‐complexity, QCA‐based one‐bit digital comparator circuit for the ultra‐nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer‐E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

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Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology

Cited by 16 publications

References 17 publications

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Parity Generators for Nanocommunication Systems Using QCA Nanotechnology

Single‐bit digital comparator circuit design using quantum‐dot cellular automata nanotechnology

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