Design of Real-time Convolution Processor and its Application in Radar Echo Signal Simulator

Abstract

An approach of implementing time-domain realtime convolution processor into multi-chip FPGA hardware platform is stated and the application of the convolution processor in radar echo signal simulator is introduced. With high speed input data flow, the algorithm of parallel-decomposition and coefficientpartitioned convolution is proposed to meet the realtime requirement. With the decomposition of the input data and the coefficient sequence, the input data flow from ADC with high sample rate can be slow down; with the partition of the coefficient sequence, the overall convolution process can be partitioned into several sub-convolutions and implementing into multichip FPGA hardware platform. The algorithm and design architecture shown in the paper is useful in complicate radar echo signal simulation with broadband coverage and low input-output delay.