Research and implementation of a large-bandwidth real-time radar jamming simulator

Abstract

The electromagnetic environment faced by modern radar is becoming increasingly complex. One effective means to improve the performance of radar systems is testing in an anti-jamming ability test chamber, where the increased complexity has also led to higher performance requirements for radar jamming simulators. Based on the requirements for modern radar system testing, this paper presents a study of a large-bandwidth real-time radar jamming simulator and describes its overall design architecture; the simulator covers the L-Ku and Ka frequency bands and the instantaneous bandwidth is ≥2 GHz, which means that the system is able to simulate 11 interference patterns. Synchronous control of the system is realized in 1 ms through use of the reflection memory interrupt mechanism, the synchronous pulse signal mechanism, synchronous timing design, and a real-time control software architecture. An overall design scheme for real-time simulation of a radar target jamming echo is given and baseband signal processing resources are saved through information preprocessing, a large-capacity high-speed storage board is designed to improve the data reading speed, a multiphase filtering structure is used to achieve high sampling rates and save hardware resources, and a high-speed parallel computing method is used to improve computing efficiency; the actual measured baseband signal processing time is less than 500 ns. Finally, a measurement platform is built, and the main interference patterns are verified through experimental measurements.