Design of quaternary MIN and MAX circuits using graphene nanoribbon field effect transistors

Basha, Shaik Javid; Venkatramana, P

doi:10.1016/j.matpr.2022.06.394

Cited by 9 publications

(2 citation statements)

References 14 publications

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“…In recent days, the ternary logic provides degraded chip complexity, reduced wire length and transmits large data compared to conventional logic. 3,4 Conventionally, the ICs are implemented utilizing the binary logics which consists of logic states 0 and 1 equivalent to voltages 0 and V DD , respectively. The ternary have three states 0, 1, and 2 equal to voltages 0, V DD /2 and V DD , respectively.…”

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confidence: 99%

Analysis of Crosstalk Effects for Ternary Logic MWCNT Bundled Through Silicon Vias

Basha¹,

Venkatramana²

2023

ECS J. Solid State Sci. Technol.

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We present a technique to improve the crosstalk effects in ternary coupled through silicon vias (TSVs). The effects of crosstalk were investigated in TSVs using multi-walled carbon nanotube (MWCNT) as metallic liner and polymers such as polyimide, polypropylene carbonate, and benzocyclobutene (BCB) as dielectric liners. The circuit model for coupled TSVs driven by a ternary inverter was utilized to analyze the various crosstalk issues. The HSPICE tool was utilized to develop the proposed TSVs. The crosstalk issues for the MWCNT TSVs were investigated and compared to single-walled CNT (SWCNT) TSVs. Moreover, the power, power delay product, and energy delay product were analyzed and compared to SWCNT TSVs. All of the performances were also studied for different TSV pitches. The coupled TSVs with BCB showed high performance for the large pitch values. Moreover, it was noted that the coupled TSVs with BCB at 5000μm TSV pitch improved the performance up to 40.03% over the SWCNT TSVs.

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confidence: 99%

Analysis of Crosstalk Effects for Ternary Logic MWCNT Bundled Through Silicon Vias

Basha¹,

Venkatramana²

2023

ECS J. Solid State Sci. Technol.

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“…In recent days, the binary logic is replaced with the ternary logic because of its various advantages such as high speed, reduced computations and high bandwidth. [6][7][8][9] The ternary logic comprises three logics 0, 1 and 2 that are describes the voltages 0 V, 0.5 V DD and V DD , respectively. The comparative study of binary logic and ternary logic multiplier is presented in Ref.…”

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confidence: 99%

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

Ratankumar

2022

ECS J. Solid State Sci. Technol.

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A novel method is presented for design of ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed, and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter, positive inverter, and negative inverter and ternary basic gates such as AND, NAND, OR, and NOR gates are designed. Furthermore, half adder circuits are developed, which assists in the development of complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Finally, the performance of the proposed circuits are investigated in terms of delay, power dissipation, and power delay product and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

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