Design of Power and Area Efficient Approximate Multipliers

Venkatachalam, S.; Ko, Seok‐Bum

doi:10.1109/tvlsi.2016.2643639

Cited by 276 publications

(113 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…19,29,30 Priyatharshne et al 26 presented an optimized Wallace tree multiplier that used parallel multipliers to reduce the iterative computation. 19,29,30 Priyatharshne et al 26 presented an optimized Wallace tree multiplier that used parallel multipliers to reduce the iterative computation.…”

Section: Related Workmentioning

confidence: 99%

“…Various techniques have been reported from conventional Wallace tree multipliers 20,26-28 and approximate multiplier implementations. 19,29,30 Priyatharshne et al 26 presented an optimized Wallace tree multiplier that used parallel multipliers to reduce the iterative computation. It also used Han-Carlson adder algorithm, 31 which reduced the overall latency.…”

Section: Related Workmentioning

confidence: 99%

“…Another approximate multiplier presented by Venkatachalam et al 29 based on altering the partial products by applying probability. For both multipliers, OR gate is applied on the altered partial products and then added using approximate half, full adders, and 4-2 compressor.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

High‐performance low‐power approximate Wallace tree multiplier

Abed

Khalil

Modhaffar

et al. 2018

Circuit Theory & Apps

View full text Add to dashboard Cite

Multipliers are considered critical functional units in many systems like DigitalSignal Processing (DSP), machine learning, and so on. The overall performance of such systems are dependent on the efficiency of multipliers. However, multipliers are slow and power inefficient components due to their complex circuits, so we aim to reduce their power consumption by relaxing their accuracy requirements and at the same time enhancing their speed. In this paper, we present a fast and a power-aware multiplier that targets error-resilient systems. This is achieved by using our proposed approximation algorithm, a hybrid Wallace tree technique for reducing power consumption, and a hybrid ripple-carry adder for reducing latency. The proposed approximation algorithm is implemented using both a modified bit-width aware and carry-in prediction technique, while the proposed hybrid Wallace tree is implemented using high order counters. These proposed algorithms are implemented using HDL language, synthesized, and simulated using Quartus and Modelsim tools. For a 16-bit multiplier, a mean accuracy of 98.35% to 99.95% was achieved with a 45.77% reduction in power, a 21.48% drop in latency, and a 34.95% reduction in area. In addition, our design performs even better for larger size multipliers (32bit multiplier) where a 61.24% reduction in power was achieved, with an 8.74%drop in latency and a 35.24% reduction in area with almost no loss in accuracy. /journal/cta to overcome common performance metrics such as area, speed, and/or power consumption. Booth algorithm, 1 Wallace tree, 2,3 Dadda tree, 4 and array multiplier 5 are examples of such designs. Wallace tree multiplier is one of the best parallel designs used to reduce the multiplier's latency by adding partial products in parallel.Applications including multimedia, 6 neural networks, 7 DSP filtering, 8 and machine learning are error tolerant and do not require a perfect accuracy in computation; hence, getting an approximate result is sufficient. In multimedia applications, as an example, getting precise results is not always required because human observation is limited. For such applications, implementations can be relaxed in order to reduce power consumption, accelerate computations, and minimize area, thus, achieving better performance. Approximate computing is an emerging computing paradigm to enhance the performance of error-tolerant applications. 9-11 According to Han and Orshansky, 10 applications suitable for approximate computing can be classified into four classes: applications with analog inputs, applications with analog outputs, applications with no unique answers, and lastly iterative and convergent applications.Adders and multipliers are the two main components used for approximations. Many research works have been conducted on approximate implementations that are based on adders and can be found in Gupta et al, Zhu et al, On the other hand, fewer works exist in the field of approximate multipliers. Some algorithms used for approximate multipliers are truncation, ...

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

High‐performance low‐power approximate Wallace tree multiplier

Abed

Khalil

Modhaffar

et al. 2018

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…One of the primary applications for approximate computing is the approximate multipliers. Several approximate multiplier designs were proposed in the literature such as [3][4][5][6]. Using these multipliers can lead to significant performance enhancements.…”

Section: Introductionmentioning

confidence: 99%

“…In a previous work [7], we have studied the impact of using approximate multipliers on the inference stage of a pre-trained CNN network. The simulated MRE and SD in [7] were selected to approximately simulate the reported inaccuracies by various approximate multipliers in the literature such as [3][4][5][6]. The work in [7] has demonstrated that with minimal cost of added inaccuracy, approximate multipliers can be used to enhance to significantly boost the inference performance of a pre-trained deep convolutional neural network (CNN) in terms of speed, power, and area.…”

Section: Introductionmentioning

confidence: 99%

Deep Learning Training with Simulated Approximate Multipliers

Hammad

El‐Sankary

2019

2019 IEEE International Conference on Robotics and Biomimetics (ROBIO)

View full text Add to dashboard Cite

This paper presents by simulation how approximate multipliers can be utilized to enhance the training performance of convolutional neural networks (CNNs). Approximate multipliers have significantly better performance in terms of speed, power, and area compared to exact multipliers. However, approximate multipliers have an inaccuracy which is defined in terms of the Mean Relative Error (MRE). To assess the applicability of approximate multipliers in enhancing CNN training performance, a simulation for the impact of approximate multipliers error on CNN training is presented. The paper demonstrates that using approximate multipliers for CNN training can significantly enhance the performance in terms of speed, power, and area at the cost of a small negative impact on the achieved accuracy. Additionally, the paper proposes a hybrid training method which mitigates this negative impact on the accuracy. Using the proposed hybrid method, the training can start using approximate multipliers then switches to exact multipliers for the last few epochs. Using this method, the performance benefits of approximate multipliers in terms of speed, power, and area can be attained for a large portion of the training stage. On the other hand, the negative impact on the accuracy is diminished by using the exact multipliers for the last epochs of training.

show abstract

A study on VLSI implementation of image enhancement techniques

Aklak

Pugazhenthi²,

Alex

2021

Concurrency and Computation

View full text Add to dashboard Cite

In real-time, the images captured are not always appreciable for visual perception.The quality of the image relies on the illumination condition. Contrast enhancement is required to improve the visual quality of the image. In this article, the image enhancement techniques that are adaptable for real-time images are studied. Further, an investigation is done on implementing the image processing algorithms in very large-scale integration (VLSI) hardware. As the image data are comparatively larger, the computational complexity and the memory requirement are more. From the study, the need for efficient computation of such image processing algorithms is realized. The efficient computation of image processing algorithms on hardware platforms, in particular on field programmable gate array (FPGA), is reviewed. As an experiment, the gamma-transformation technique used for image enhancement is realized. Initially, the prototype is modeled using MATLAB, and then it is implemented using an FPGA. K E Y W O R D Sfield programmable gate array, floating point multiplier, image enhancement INTRODUCTIONIn the modern digital world, all multimedia transactions require good-quality images. The visibility of an image depends on the illuminance and reflectance of the scene in the real world. The brightness of a point in an image is non-linear to the brightness of the same point in the real world.Generally, lighting condition determines the quality of an image. The images taken under poor lighting conditions may cause discomfort while viewing images.The image acquired can be degraded due to various reasons such as sensor level malfunction, low visibility, excessive exposure, foggy conditions, and so on. 1 To overcome the degradation, pre-processing is required to enhance the image. Image enhancement is the process of adjusting digital images so that the results are more suitable for display or further processing. It includes processes like deblurring, noise removal, filtering, and so on.Not all images will require the same image enhancement technique because there may be over-exposed regions in outdoor images that will need different treatment compared to indoor images. In literature, there are many algorithms proposed for image enhancement. The technique of being applied for enhancement depends on the input quality of the image. The quality needs to be assessed before applying any approach for a better perception of the image. A real-time implementation of image enhancement is hard to design using software because a large data set is required to represent an image. Since field programmable gate arrays (FPGAs) could exploit the spatial parallelism in image enhancement algorithms they are widely used for hardware implementation.Realizing the design on FPGAs, offer a compromise between the flexibility of general-purpose processors and the hardware-based speed of an integrated-circuit design. 2 Also, the programmable property of FPGA makes them a good choice for image processing applications, as the processing of the number of images also...

show abstract

Design of Power and Area Efficient Approximate Multipliers

Cited by 276 publications

References 10 publications

High‐performance low‐power approximate Wallace tree multiplier

High‐performance low‐power approximate Wallace tree multiplier

Deep Learning Training with Simulated Approximate Multipliers

A study on VLSI implementation of image enhancement techniques

Contact Info

Product

Resources

About