Design of optimized high Q inductors on SOI substrates for RF ICs

Royet, A.S.; Michel, Jean‐Philippe; Reig, B.; Pornin, Jean-Louis; Ranaivoniarivo, Manohiaina; Robain, B.; Person, P.; U'Ren, Gregory

doi:10.1109/icecs.2016.7841198

Cited by 9 publications

(8 citation statements)

References 7 publications

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“…Maximum output power and power conversion efficiency were taken into account as the most important parameters of the converter circuit and only inductance, series resistance and quality factor was considered for ideal integrated inductor. Three different values of inductance and series resistance for the ideal inductor were chosen with respect to measurements presented in [4] and other works [5], [7]. The inductance values L 1 = 36.871 nH, L 2 = 42.431 nH and L 3 = 66.086 nH were used.…”

Section: Achieved Resultsmentioning

confidence: 99%

Investigation of Inductor-based Fully On-chip Boost Converter

Robert

Arbet

Kovac

et al. 2021

2021 28th International Conference on Mixed Design of Integrated Circuits and System

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This paper presents the efficiency investigation of a fully on-chip DC-DC step-up converter realized in a standard 130 nm CMOS technology and its comparison to previous works. Research is mainly focused on finding the optimum operation point to provide the high output power and conversion efficiency of the on-chip converter solution. The obtained output voltage of 1.2 V shows 98.6 % efficiency of power conversion, and the maximum output power of 6 mW is achieved. Another performed analysis has been focused on impact of inductor properties as well as impact of the control circuit on the main parameters of the developed boost voltage converter.

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Section: Achieved Resultsmentioning

confidence: 99%

Investigation of Inductor-based Fully On-chip Boost Converter

Robert

Arbet

Kovac

et al. 2021

2021 28th International Conference on Mixed Design of Integrated Circuits and System

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“…3. Basic schematic of DC-DC step-up converter of quality factor for inductor were Q 1 = 3, Q 2 = 9 and Q 3 = 15, based on the proposed inductor and inductors in [8]. All configurations were designed and simulated using Cadence environment with frequency in the range from 100 MHz to 800 MHz and for 130 nm CMOS technology.…”

Section: Achieved Resultsmentioning

confidence: 99%

“…2(d)was then captured and used in the simulations of the converter efficiency. Values of quality factor were chosen with respect to technology and another sources[8].…”

mentioning

confidence: 99%

Feasibility study towards increasing efficiency of fully on-chip DC-DC boost converter

Robert

Arbet

Kovac

et al. 2020

2020 International Conference on Applied Electronics (AE)

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In this paper, an investigation of the efficiency of fully on-chip DC-DC step-up converter realized in a standard 130 nm CMOS technology is presented. The converter has been designed for regulated output voltage of 1.2 V with an on-chip inductor and an output capacitor. The obtained results show that the proposed on-chip converter can achieve the efficiency up to 98 % and the output power up to 6 mW. The performed analysis investigates possibilities for the further improvement focused on the maximum efficiency and output power.

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“…Due to the induced eddy current, the net current distribution on the metal strip concentrates on the inner edge of the strip and, thus, increases the metal resistance. To mitigate the influence of the eddy current, inductor designs with variable line widths and/or line spacing layouts have been presented [14][15][16][17][18][19][20][21][22][23][24][25]. Figure 1 shows the layout of a spiral inductor with a variable line width design.…”

Section: Introductionmentioning

confidence: 99%

Analytic Design of on-Chip Spiral Inductor with Variable Line Width

Chen¹,

Hsu²

2022

Electronics

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On-chip spiral inductors with variable line width layouts are known for their high quality factor (Q-factor). In this paper, we present an analytical approach to facilitate the design of such inductors. Based on an analysis of ohmic and eddy-current losses, we first derive an analytical formula for the metal resistance calculation of a spiral inductor. By minimizing the metal resistance, a simple design equation for finding the proper line width of each coil is then presented. Several 0.18 μm CMOS spiral inductors are investigated, via electromagnetic simulations and experimental studies, to test the proposed resistance calculation, as well as the variable line width design method. It is found that the developed resistance calculation can effectively model the metal-line resistance of a spiral inductor. Moreover, the inductor with a variable line width obtained using the proposed method can significantly improve the Q-factor with little compromise to inductance, which validates the capacity of the developed variable line width design technique. Since the proposed approach can be carried out using analytical calculations, it may be a more efficient design method than those previously reported in the literature.

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Design of optimized high Q inductors on SOI substrates for RF ICs

Cited by 9 publications

References 7 publications

Investigation of Inductor-based Fully On-chip Boost Converter

Investigation of Inductor-based Fully On-chip Boost Converter

Feasibility study towards increasing efficiency of fully on-chip DC-DC boost converter

Analytic Design of on-Chip Spiral Inductor with Variable Line Width

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