Design of one-transistor SRAM cell for low power consumption

Yadava, Narendra; Mishra, Vimal Kumar; Chauhan, R. K.

doi:10.1109/iceteeses.2016.7581401

Cited by 4 publications

(3 citation statements)

References 16 publications

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“…At the low level, examples of approaches for power savings include different SRAM configurations [7] or using low power modes in network devices, for example in periods of low activity using lower power modes (sleep mode) in some components on LAN switches [8,9].…”

Section: Literature Reviewmentioning

confidence: 99%

LAWA: Loss-Aware Workload Assignment in Data Centers

Esmaeilnezhad

Down

2021

2021 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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Section: Literature Reviewmentioning

confidence: 99%

LAWA: Loss-Aware Workload Assignment in Data Centers

Esmaeilnezhad

Down

2021

2021 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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“…Therefore, they will retain their mainstream position in the memory industry for the foreseeable future. Technologies have been proposed to solve the aforementioned limitations of traditional memory devices, such as removing the storage capacitor of DRAM and reducing the number of transistors of SRAM …”

Section: Introductionmentioning

confidence: 99%

“…Technologies have been proposed to solve the aforementioned limitations of traditional memory devices, such as removing the storage capacitor of DRAM [16,17] and reducing the number of transistors of SRAM. [18] In this study, we demonstrate a switchable-memory transistor with a p + -i-n + doped silicon nanowire whose fabrication process is fully compatible with silicon-based complementary metal-oxide semiconductor (CMOS) technology. The outstanding memory characteristics originate from the positive feedback loop in the intrinsic channel.…”

mentioning

confidence: 99%

Switchable‐Memory Operation of Silicon Nanowire Transistor

Kim

Cho

Lim

et al. 2018

Adv Elect Materials

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of conventional memory are advantages of SRAM and DRAM over new alternatives. Therefore, they will retain their mainstream position in the memory industry for the foreseeable future. Technologies have been proposed to solve the aforementioned limitations of traditional memory devices, such as removing the storage capacitor of DRAM [16,17] and reducing the number of transistors of SRAM. [18] In this study, we demonstrate a switchable-memory transistor with a p + -i-n + doped silicon nanowire whose fabrication process is fully compatible with silicon-based complementary metal-oxide semiconductor (CMOS) technology. The outstanding memory characteristics originate from the positive feedback loop in the intrinsic channel. Notably, our single device not only reduces the number of transistors (constituting a single SRAM cell) in the memory device but also operates the switching function. This is one of the novel strengths of our switchable-memory device for future electronics, as conventional memory devices only provide the function of data storage. The decrease in the number of transistors and the operation of multiple functions can be beneficial for scaling the memory device with regard to the total chip size and power consumption. Hence, we propose a feedback field-effect transistor (FET) with a dual top-gated silicon nanowire channel to enable the switching and memory functions in a single transistor. Results and DiscussionWe demonstrate the switchable-memory characteristics of a silicon nanowire transistor with a dual-gate structure. Figure 1 shows schematic and optical images of our transistor, which consists of a silicon nanowire channel and dual-gate electrodes. On the upper side of the channel region (6 µm long), two gate electrodes (each 2 µm wide) are arranged side by side. The gate electrode located near the p + doped region is named "Gate1 (V G1 )," and the other gate electrode located near the n + doped region is named "Gate2 (V G2 )." Details regarding the fabrication are presented in Experimental Section. Our switchable-memory transistor can be fabricated using conventional CMOS technology, which is clearly advantageous for industrial applications.As shown in Figure 2a, when V DS is swept from −0.1 to 4.1 V and then back to −0.1 V as a function of V G1 and V G2 , our transistor shows bistable I DS -V DS characteristics owing to the similar structures of thin capacitively-coupled thyristor (TCCT) devices [19][20][21] and field-effect diodes. [22,23] Without gate bias voltages, the transistor exhibits ordinary p-n diode characteristics;The switchable-memory operation of a feedback silicon nanowire transistor with a dual-gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec −1 . A gate-controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more th...

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