Design of non‐restoring divider in quantum‐dot cellular automata technology

Abstract

Among all basic arithmetic operations, the division is the most complex one. On the other hand, working onpost-complementary metal-oxide-semiconductor (CMOS) technology attracts attention of many researchers, while theprogress of miniaturisation in CMOS technology faced physical limits. Therefore, in this study, the authors propose anon-restoring divider in quantumdot cellular automata (QCA), as one of the most promising technology. To achieve anefficient divider, they propose a novel 1 bit full-adder and take advantage of improved design of XOR gate. This designhas considerable improvements in terms of cell numbers, delay and area, compared with other dividers. Thesuggested design is simulated in QCADesigner software and acceptable results are achieved. Floppy Drive-1.

Adiabatic Hamming Code Generator-Checker using 4-Dot-2-Electron Quantum Dot Cellular Automata

“…The clocking sequence for the XOR gate of [8] is provided in Table I. Figure 4 through Figure 7 present the QCA realization for Equation (4) through (7). The designs have been implemented using QCA Designer [9] using Bistable Approximation as the Simulation Engine.…”

“…This communication explores the viability of QCA cells in designing cryptographic architectures, explicitly the Hamming Code Generator and the Checker. Boolean XOR operation forms the foundation for cryptographic designs; hence, we explore numerous XOR proposals using QCA cells in literature [6] [7] and concentrate on a state-of-the-art design [8] for designing the novel Hamming Code Generator-Checker in this work. The design exhibits better results in peer comparison and reflects optimized performance when implemented using [9].…”

High‐performance full adder architecture in quantum‐dot cellular automata

“…The prime contribution on the QCA‐based logic circuits have been developed by optimisation of the parameters such as layout complexity (cell count), effective area, and clock delay (number of clock zones) to achieve high efficiency and quality of the designs. Recently, several promising designs have been presented such as efficient QCA full adder designs [3, 5–39], flip‐flops, and memory structures [36, 40, 41], efficient QCA multiplier designs [42, 43], encoder/decoder circuits [44], and efficient QCA multiplexer designs [19, 45, 46].…”

“…Full adder has a key role in many computational circuits design such as implementation of multiplier [35], and arithmetic logic unit [46]. Up to now, many efforts have been made to improve the performance of the full adder in the QCA technology [3, 5–39].…”

A Universal Reversible Gate Architecture for Designing N-Bit Comparator Structure in Quantum-dot Cellular Automata

“…The existing CMOS has been under constraints by the growing QCA technology as consider to high-speed operating frequency and low power are involved [4]. The cost and complexity of a QCA design are particularly affected by the cell count, area, and latency.…”