Design of new full adder cell using hybrid-CMOS logic style

Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications

“…The first category of full adders is based on XOR gates (XOR-XOR based full adder) and second one is based on XNOR gates (XNOR-XNOR based full adder). In third category, the Sum and Carry outputs are generated by XOR-XNOR intermediate signals (Zavarei et al, 2011) (centralized full adder). In M this paper, the proposed full adder stand on third category.…”

“…The simultaneous generation of H and H' signals is critical in these types of adders, because they drive the select lines of the multiplexers in the output stage. Otherwise, there may be glitches and unnecessary power dissipation may be occur (Zavarei et al, 2011).…”

“…A minimum output load of fan-out of four inverters (FO4) is used for power and delay measurements (Goel et al, 2006), the value of which amounts to 1.234fF (about 0.308fF for each inverter in 65nm technology). The generic simulation test bench used is shown in Figure 4 along with the transistor sizes of each buffer (Zavarei et al, 2011). To reach more accurate results, all transitions from an input combination to another (56 patterns) have been tested, and the delay at each transition has been measured.…”

“…In the other full adder designs, more than one logic style have been used. These designs are called hybrid-CMOS logic style (Zavarei, Baghbanmanesh, Kargaran, Nabovati, & Golmakani, 2011). These designs use the features of different logic styles to improve upon the performance of the designs using single logic style.…”

“…These designs use the features of different logic styles to improve upon the performance of the designs using single logic style. HPSC full adder (hybrid pass logic with static CMOS output drive full adder) (Zhang, Gu, & Chang, 2003), New-HPSC adder (Chang, Gu, & Zhang, 2005), New-Hybrid-CMOS adder (Goel, Kumar, & Bayoumi, 2006), and full adders proposed in (Zavarei et al, 2011), (Musala & Reddy, 2013), (Lin, Hwang, & Sheu, 2012) and (Agarwal, Agrawal, & Alam, 2014), are the examples of adders designed with this logic style. In this paper, a novel 1-bit full adder has been proposed with better performance in comparison with New-HPSC, New-Hybrid-CMOS adders, and full adders proposed in (Zavarei et al, 2011), (Musala & Reddy, 2013), (Lin et al, 2012) and (Agarwal et al, 2014).…”