Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications

Abstract

This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. Using a novel structure for implementation of the proposed full adder caused it has better performance in terms of propagation delay and power-delay product (PDP) compared to its counterparts. According to the simulation results, the propagation delay of the proposed full adder is 22.8% less than the propagation delay of next fastest full adder, and the power-delay product of the proposed full adder is 22.7% less than the next best PDP. HSpice simulations using 65nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits.