Design of Multipliers using Reversible Logic and Toffoli Gates

Autade, Prerana P.; Turkane, S. M.; Deshpande, Anupama

doi:10.1109/esci53509.2022.9758329

Cited by 5 publications

(4 citation statements)

References 12 publications

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“…Autade et al, [20] presented a multipliers design utilizing Reversible Logic with Toffoli gates. For designing the Baugh-Wooley Multiplier, first the full adder circuit using the multiple controlled reversible gates was designed.…”

Section: Literature Surveymentioning

confidence: 99%

“…Xpower analysis tool is used to calculate the power. Then the performance of the proposed FPGA-BWM-MCT-MCF method is compared with the existing designs, like FPGA-BWM-RL-TG [20], FPGA-BWM-TG-FG [21].…”

Section: Fpga Implementation Of Proposed Baugh Wooley Multipliermentioning

confidence: 99%

“…This manuscript concentrates on delay, garbage output, constant input, quantum costs and power calculation parameters. [20], High speed low power multipliers depending on reversible logic Toffoli Gate (TG) and Feyman gate (FG) (BWM-TG-FG) [21], respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device.…”

Section: Introductionmentioning

confidence: 99%

“…The performance of the proposed FPGA-BWM-MCT-MCF approach is analyzed with the existing designs, like multipliers design utilizing Reversible logic with Toffoli gate (FPGA-BWM-RL-TG) [20], Higher speed lower power multipliers based on reversible logic (FPGA-BWM-TG-FG) [21].…”

Section: Introductionmentioning

confidence: 99%

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Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Raj

Kumar

Satyanarayana

2023

IRASE

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Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

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Section: Literature Surveymentioning

confidence: 99%

Section: Fpga Implementation Of Proposed Baugh Wooley Multipliermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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