Reversible logic gates, which are proven to provide zero power dissipation under ideal conditions, are in high demand for future computing technologies. Using reversible logic gates, this study provides an improved design for a low-cost 4X4 multiplier circuit module. The module can implement 8x8, 16x16 and up higher order multiplier circuits. In terms of gate counts, garbage outputs, constant inputs, and quantum cost, the suggested multiplier circuit using minimum number of half adders and full adders excels existing designs, presented using a comparative table. Moreover, this concept can be used to implement different complex systems in the field of nanotechnology. With the aid of the final output generation table, the proposed reversible circuit's operation is analyzed step-by-step in this article. Additionally, an RTL design of the suggested multiplier circuit is shown, followed by a simulation waveform that illustrates how the design works. Additionally, utilizing the Xilinx ISE 14.7 software tool, experimental outcomes based on the on-chip power, delay, and other relevant parameters are evaluated.
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