Design of multichip modules

Schaper, L.W.

doi:10.1109/5.192075

Cited by 27 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Applying the Galerkin weighted residual integrals to equation (1) as shown by Schaper (1992) and Lewis et al (1996) Equation 9 leads to Equation 10 for an element, where Equation 11 where a is the half width of rectangular element; b is the half height of rectangle element; K x and K y are the thermal conduction coefficient; h is the heat transfer coefficient; A is the area of a rectangular element (4ab).…”

Section: The Model For Thermal Management Of MCM and Pcbmentioning

confidence: 99%

See 1 more Smart Citation

Thermal management of multi‐chip module and printed circuit board using FEM and genetic algorithms

Jeevan

Quadir

Seetharamu

et al. 2005

Microelectronics International

View full text Add to dashboard Cite

PurposeTo determine the optimal chip/component placement for multi‐chip module (MCM) and printed circuit board (PCB) under thermal constraint.Design/methodology/approachThe placement of power dissipating chips/component is carried out using genetic algorithms (GA) in order to achieve uniform thermal distribution on MCM and PCB. The thermal distribution on the MCM and PCB are predicted using 2D‐finite element method (FEM) analysis. Different number of chip/component and FEM meshing size is used to investigate the placement of chips/components.FindingsThe optimal placement of chip/component using GA is compared well to other placement techniques. The coarse meshing for FEM employed here is found adequate to carry out optimal placement of components by GA.Research limitations/implicationsThe analysis is valid for constant properties of MCM or PCB and steady state conditions. The chip/component size is limited to a single standard size.Practical implicationsThe method is very useful for practical design of chip/component placement on MCM/PCB under thermal consideration.Originality/valueFEM analyses of MCM and PCB can be easily implemented in the optimization procedure for obtaining the optimal chip/component placement based on thermal constraints.

show abstract

Section: The Model For Thermal Management Of MCM and Pcbmentioning

confidence: 99%

“…The thermal distribution within the substrate creates a problem for thermal management of MCM's (Bar‐Cohen, 1987). The thermal performance must be accurately predicted during the design phase to maintain satisfactory reliability (Schaper, 1992).…”

Section: Introductionmentioning

confidence: 99%

Thermal management of multi‐chip module and printed circuit board using FEM and genetic algorithms

Jeevan

Quadir

Seetharamu

et al. 2005

Microelectronics International

View full text Add to dashboard Cite

show abstract

“…Multi-chip module (MCM) technology becomes another candidate [17]. Nevertheless, the quality of MCM-L integrated passives are relatively poor and limited to low frequencies [18] and may waste a large connection area because of wide line and separation width [19]. Although hybrid technology is also a candidate [20], [21], they occupy large areas and special consideration may be required for connections and arrangement of parts to prevent degradation of its characteristics [22], [23].…”

Section: Introductionmentioning

confidence: 99%

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

Sudou

Takao²,

Sawada³

et al. 2007

IEEE Trans. Comp. Packag. Technol.

View full text Add to dashboard Cite

This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of SMDs. A non-conductive adhesive (CYTOP) are coated on the deep holes and it is used to fix the aligned SMDs. SMDs are distributed on a Si-wafer mounted on vibration generator, and then a vibration is applied. The SMDs migrate due to the reduced friction between the wafer surface, and they drop into the holes on the silicon wafer. The size of the holes has an appropriate clearance to the size of SMD. In order to align two or more kinds of SMDs, sizes of the deep holes on a Si-wafer are adjusted to the size of each SMD. SMDs with the largest size are dropped into the holes first, and then the secondary large SMDs are dropped into the holes with the corresponding size. SMDs are finally connected electrically by wire bonding at the final step. In the experiment, two different sizes of SMD were successfully mounted into all the holes on a Si-wafer automatically. This technology will be a wafer-level process technology which is very promising to integrate two or more kinds of discrete elements.Index Terms-Embedded passive integrated circuits (emPIC), passive integration, silicon integrated circuit (IC) technology.

show abstract

“…Applications range from portable computer and communications devices to missile, aeronautical, and satellite based processors. Increasingly, these applications are moving towards a stacked MCM architecture to provide a large amount of processing power in a small volume 9,10 .…”

Section: 1ci Multichip Module Interconnectsmentioning

confidence: 99%

Optically Guiding Substrates for Low Cost Optical Interconnects in Stacked Multichip Module and Chip Scale Packaging

Haas¹,

Cook²

1998

View full text Add to dashboard Cite

Public reporting burden for this collection of information is estimatedApproved for public release; distribution unlimited. 12b. DISTRIBUTION CODE ABSTRACT (Maximum 200 words)A novel method of integrating an optically guiding material into the support structure of the computer creates a high performance data buss while reducing the complexity and cost of implementing an optical interconnect scheme. This report discusses the use of optically guiding materials in both multichip module and chip-scale packaging schemes. In both implementations, closely spaced optical data channels are guided from one plane of electronic circuits to another without the need of costly micro-optics and complex alignment requirements. Table of Figures ii Table of Tables iii Abstract iv SUBJECT TERMS

show abstract

Design of multichip modules

Cited by 27 publications

References 7 publications

Thermal management of multi‐chip module and printed circuit board using FEM and genetic algorithms

Thermal management of multi‐chip module and printed circuit board using FEM and genetic algorithms

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

Optically Guiding Substrates for Low Cost Optical Interconnects in Stacked Multichip Module and Chip Scale Packaging

Contact Info

Product

Resources

About