Design of low power system on programmable chip for video zoom-in processing

Touil, Lamjed; Kechiche, Lilia; Ouni, Bouraoui

doi:10.3906/elk-1408-84

Cited by 2 publications

(3 citation statements)

References 18 publications

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“…In previous works [20,21], we suggested various real-time video processing architecture with a variety of power saving techniques. In [20] the authors put forward a hardware architecture for video zoom-in processing with power reduction.…”

Section: Hardware Software Architecture For Real-time Video Processingmentioning

confidence: 99%

“…In [20] the authors put forward a hardware architecture for video zoom-in processing with power reduction. The proposed hardware architecture was based on the MicroBlaze 32-bit microprocessor and uses the Processor Local Bus (PLB), an ancient protocol adopted by Xilinx before moving to the Advanced eXtensible Interface (AXI) protocol.…”

Section: Hardware Software Architecture For Real-time Video Processingmentioning

confidence: 99%

See 1 more Smart Citation

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

Kechiche

Touil

Ouni

2018

International Journal of Reconfigurable Computing

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Driven by the importance of energy consumption in system-on-chip design as an evaluation factor, this paper presents a design methodology at the system level to optimize power consumption on ARM-based architecture for real-time video processing. The proposed design flow is based on the interaction between the tool and user optimizations. The tool optimizations are the options and best practices available on the integrated design environment for the Xilinx technology and the target Zynq-7000 architecture. The user methods present methods proposed by the user to optimize power consumption. We used the principles of voltage scaling and frequency scaling techniques for user methods. These two techniques allow energy to be consumed in the proportion of work to be done. The suggested flow is applied on real-time video processing system. The results show power savings for up to 60% with respect to performance and real-time constraints.

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Section: Hardware Software Architecture For Real-time Video Processingmentioning

confidence: 99%

Section: Hardware Software Architecture For Real-time Video Processingmentioning

confidence: 99%

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

Kechiche

Touil

Ouni

2018

International Journal of Reconfigurable Computing

Self Cite

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“…We find in the literature other work exploring how to design a low power system on FPGAs. For example, in [6] the authors investigated design optimization to improve FPGA performance. They developed a typical design for video zoom-in processing with low power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support

Chtourou¹,

Marrakchi²,

Amouri³

et al. 2017

Turk J Elec Eng & Comp Sci

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Abstract:Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits. FPGA design's big challenge is to find a good trade-off between flexibility and performance in terms of power dissipation, area density, and delay. This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies. Based on experimental method and benchmarks circuit implementation, this work provides a detailed exploration and analyses of the effect of cluster functionality on the proposed cluster-based FPGA in terms of power dissipation, area density, and delay. The exploration results showed that architecture with high cluster size provides high speed performance and low power dissipation. We noted also that architecture with small cluster size is more efficient in terms of area. Look-up-table (LUT) exploration showed that using architecture with 4-input LUT offers the best trade-off between power dissipation, area density, and delay.

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Design of low power system on programmable chip for video zoom-in processing

Cited by 2 publications

References 18 publications

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support

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