Design of Low-Power Coarse-Grained Reconfigurable Architectures

Kim, Yoonjin; Mahapatra, Rabi

doi:10.1201/b10471

Cited by 6 publications

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“…The average application speedup is 2.48 for all microprocessor systems and all applications. Such amounts of speedups were also considered as important in previous works considering a processor extended with a coarsegrained reconfigurable data-path as in [10], [11]. We also mention that the reported speedups for each application and for each processor type are close to theoretical speedup bounds, especially for the ARM7 systems.…”

Section: Resultssupporting

confidence: 60%

“…In [9], a PipeRench architecture clocked at 100MHz and composed by 8-bit PEs and 53 128-bit stripes, improved on average the execution time by 12% and 7.2% for the PGP data encryption algorithm and for JPEG, respectively, relative to the execution on an UltraSparcII running at 300 MHz. In [10], it is shown that a hybrid architecture composed by an ARM926EJ-S and an 8x8 Reconfigurable Array similar to MorphoSys [3], executes 2.2 times faster an H.263 encoder than a single ARM926EJ-S processor. The mapping flow for the ADRES architecture was applied to an MPEG-2 decoder in [11].…”

Section: Preliminariesmentioning

confidence: 99%

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Improving Performance of Embedded Processors with a High-Performance Coarse-Grained Reconfigurable Data-Path

Galanis¹,

Dimitroulakos²,

Goutis³

MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference

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An embedded system that extends microprocessor cores with a high-performance Coarse-Grained Reconfigurable Data-Path is introduced. The data-path is composed by computational resources able to realize complex operations which aid in improving the performance of time critical application parts, called kernels. A compilation flow is defined for mapping high-level software descriptions to the microprocessor system. The kernel code is mapped using a properly developed mapping algorithm for the Reconfigurable Data-Path. Extensive exploration is performed by mapping four real-life applications on three different instances of the system. Important overall application speedups have been reported that range from 1.70 to 3.68 relative to an all-processor execution. I. PRELIMINARIESEmbedded systems have been proposed that extend the computational capabilities of a microprocessor core by coupling it with reconfigurable logic [1]. Reconfigurable hardware is used to implement computational intensive parts of the applications, called kernels. The microprocessor core executes non-critical sequential code parts and provides software programmability. The spatial parallelism present in kernels is exploited by the abundant Processing Elements (PEs) of the reconfigurable hardware, resulting in performance improvements. Reconfigurable logic allows for the adaptation of the microprocessor system to the specific requirements of an application. Reconfigurable hardware has been widely associated with Field Programmable Gate Arrays (FPGAs). An FPGA consists of an array of programmable logic cells, executing bitlevel operations, with a grid of interconnect lines running among them. However FPGAs are not the only type of reconfigurable logic. Several coarse-grained reconfigurable architectures have been introduced and successfully built [2], [3], [4]. They consist of a large number of PEs with word-level data bit-widths (like 16-bit ALUs) connected with a reconfigurable interconnect network. Their coarse granularity greatly reduces the delay, area, power consumption and reconfiguration time relative to FPGA logic at the expense of flexibility [1].In this work, we propose an extension of microprocessor cores with a high-performance coarse-grained reconfigurable data-path previously presented in [5]. The computational resources of the Reconfigurable Data Path (RDP) are able to implement complex arithmetic structures. Research in HighLevel Synthesis (HLS) [6] and Application Specific Instruction Processors (ASIPs) [7], [8] have proven that the use of complex computational structures, called templates or clusters, instead of using only primitive ones (like a single ALU) in data-paths improves performance. A template may be a specialized hardware unit or a group of chained units. The ability of the considered RDP to realize template operations aids in improving performance as it was shown in [5]. A compilation flow is also introduced for efficiently mapping applications described in high-level software to the reconfigurable system. The flow mainl...

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Section: Resultssupporting

confidence: 60%

Section: Preliminariesmentioning

confidence: 99%

Improving Performance of Embedded Processors with a High-Performance Coarse-Grained Reconfigurable Data-Path

Galanis¹,

Dimitroulakos²,

Goutis³

MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference

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“…Until now, there have been a few multi‐core architecture projects based on CGRAs [1–16] for kernel‐level parallelism [6, 7–9]. However, most of them are monotonous aggregation of several CGRAs.…”

Section: Related Workmentioning

confidence: 99%

“…On the other hand, application‐specific optimisation of embedded system becomes inevitable to satisfy the market demand for designers to meet tighter constraints on cost, performance, and power. To compromise these incompatible demands, coarse‐grained reconfigurable architecture (CGRA) has emerged as a suitable solution for embedded systems [1, 2]. It can boost the performance by adopting multiple processing elements (PEs) while it can be reconfigured to adapt to evolving characteristics of the embedded applications such as audio, video, and graphics processing.…”

Section: Introductionmentioning

confidence: 99%

Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture

Kim

Joo

Yoon

2016

IET Circuits, Devices & Systems

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Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel-level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from high energy consumption and performance bottleneck when trying to exploit the KLP because of poor resource utilisation caused by insufficient flexibility. In this study, the authors propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilisation focusing on the kernel-stream type of the KLP. In addition, they introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream based on the RSF. Experimental results show that the proposed approaches improve performance by up to 88.8% and reduce energy by up to 48.2% when compared with the conventional CGRA-based multi-core architectures.

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“…In (FPGA)-based systems. However FPGAs are not the only type of [10] Coarse-grain reconfigurable logic has been mainly proposed for…”

mentioning

confidence: 99%

Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

Galanis

Dimitroulakos

Goutis

2006 IEEE International Symposium on Circuits and Systems

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Results from mapping five real-world DSP processor executes the non-critical software parts. This type of applications on a system-on-chip that incorporates coarsepartitioning is possible in embedded systems, where the application grain reconfigurable hardware with an instruction-set is usually invariant during the lifetime of the system. Processorprocessor is presented. The reconfigurable logic is realized by a CGRA systems are present in both academia [2], [3], and in 2-Dimensional Array of Processing Elements. A mapping industry [4], [6]. These SoCs is expected to further gain importance method for improving application's performance by since the CGRAs lead to smaller execution times and lower power accelerating critical software parts, called kernels, on the consumption of critical software parts when compared with FPGAs. Coarse-Grain Reconfigurable Array is proposed. For mapping Thus, a mapping methodology like the one presented in this paper, the detected kernels on the reconfigurable logic a priorityis considered as a prerequisite for improving the performance of applications in such embedded systems. The mapping method bvrase mapplication algori as, bueto t h e n devnelop acled orataont mainly consists of the following steps: (a) profiling for detecting oaveralln reported for the five applicationss acelerato critical kernel code, (b) Intermediate Representation (IR) creation, have been reported for the five applications These overall (c) mapping algorithm for the CGRA architecture, and (d) performance improvements range from 1.27 to 3.07, with an compilation to the instruction-set processor. We emphasize to the average value of 2.16, relative to an all-software execution.mapping for CGRA architectures, since it considerably affects the performance improvements through the kernels acceleration. The I. INTRODUCTION proposed mapping algorithm for CGRAs is a priority-based (listReconfigurable architectures have received growing interest in based) one and it targets a CGRA template architecture which can the past few years [1]. Reconfigurable systems represent an model a variety of existing architectures [2], [3], [6]. intermediate approach between Application Specific Integrated In [5] the instruction-set extension of a RISC processor coupled Circuits (ASICs) and general-purpose processors. Such systems with a 4x4 XPP coarse-grain reconfigurable array is described. usually combine reconfigurable hardware with one or more Performance improvements relative to the stand-alone operation of software programmable processors. Reconfigurable processors have the RISC processor are shown for an 8x8 IDCT. However, in [5] been widely associated with Field Programmable Gate Array the mapping of a complete DSP application is not performed. In (FPGA)-based systems. However FPGAs are not the only type of [10] it is shown that a hybrid architecture composed by an reconfigurable logic. Several coarse-grain reconfigurable ARM926EJ-S and a CGRA similar to MorphoSys [3], executes 2.2 architectures have been introduced and succe...

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Design of Low-Power Coarse-Grained Reconfigurable Architectures

Cited by 6 publications

References 0 publications

Improving Performance of Embedded Processors with a High-Performance Coarse-Grained Reconfigurable Data-Path

Improving Performance of Embedded Processors with a High-Performance Coarse-Grained Reconfigurable Data-Path

Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture

Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

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